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141.发明申请公开(公告)号：US20190252390A1
公开(公告)日：2019-08-15
申请号：US15900800
申请日：2018-02-21
Inventor： Yi-Wei Chen , Pin-Hong Chen , Tsun-Min Cheng , Chun-Chieh Chiu
IPC: H01L27/108 , H01L23/532 , H01L21/3215 , H01L21/285
Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.
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公开(公告)号：US20190249297A1
公开(公告)日：2019-08-15
申请号：US15919191
申请日：2018-03-12
Inventor： Chih-Chien Liu , Pin-Hong Chen , Tsun-Min Cheng , Yi-Wei Chen
IPC: C23C16/455 , H01L21/768 , H01L23/544 , H01L21/285 , H01L21/321 , C23C16/02 , C23C16/34
Abstract: A semiconductor device includes a substrate, a dielectric layer, a first tungsten layer, an interface layer and a second tungsten layer. The dielectric layer is disposed on the substrate and has a first opening and a second opening larger than the first opening. The first tungsten layer is filled in the first opening and is disposed in the second opening. The second tungsten layer is disposed on the first tungsten layer in the second opening, wherein the second tungsten layer has a grain size gradually increased from a bottom surface to a top surface. The interface layer is disposed between the first tungsten layer and the second tungsten layer, wherein the interface layer comprises a nitrogen containing layer. The present invention further includes a method of forming a semiconductor device.
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公开(公告)号：US20190206982A1
公开(公告)日：2019-07-04
申请号：US16297733
申请日：2019-03-11
Inventor： Tzu-Chin Wu , Wei-Hsin Liu , Yi-Wei Chen , Chia-Lung Chang , Jui-Min Lee , Po-Chun Chen , Li-Wei Feng , Ying-Chiao Wang , Wen-Chieh Lu , Chien-Ting Ho , Tsung-Ying Tsai , Kai-Ping Chen
IPC: H01L49/02 , H01L27/108 , H01L29/94
Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
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公开(公告)号：US10236179B2
公开(公告)日：2019-03-19
申请号：US15099581
申请日：2016-04-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Fu-Cheng Yen , Tsung-Mu Yang , Sheng-Hsu Liu , Tsang-Hsuan Wang , Chun-Liang Kuo , Yu-Ming Hsu , Chung-Min Tsai , Yi-Wei Chen
Abstract: A method for forming an epitaxial layer on a substrate is disclosed. The method includes the steps of: providing a substrate into a chamber; injecting a precursor and a carrier gas to form the epitaxial layer on the substrate at a starting pressure; and pumping down the starting pressure to a second pressure according to a gradient during a cool down process in the chamber.
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公开(公告)号：US10211211B1
公开(公告)日：2019-02-19
申请号：US15830006
申请日：2017-12-04
Inventor： Kai-Jiun Chang , Yi-Wei Chen , Tsun-Min Cheng , Chia-Chen Wu , Pin-Hong Chen , Chih-Chieh Tsai , Tzu-Chieh Chen , Yi-An Huang
IPC: H01L29/423 , H01L29/49 , H01L29/778 , H01L29/45 , H01L21/768 , H01L21/3205 , H01L21/4763 , H01L27/108 , H01L23/532 , H01L21/02 , H01L23/535
Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a barrier layer in the trench; performing a soaking process to reduce chlorine concentration in the barrier layer; and forming a conductive layer to fill the trench.
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Patent Agency Ranking
公开(公告)号：US10158022B2
公开(公告)日：2018-12-18
申请号：US15681417
申请日：2017-08-20
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Sheng-Hsu Liu , Jhen-cyuan Li , Chih-Chung Chen , Man-Ling Lu , Chung-Min Tsai , Yi-Wei Chen
IPC: H01L29/78 , H01L29/06 , H01L29/165 , H01L29/66 , H01L21/764
Abstract: A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The second semiconductor layer includes a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute angle in the range from about 10° to about 55°. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.
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公开(公告)号：US20180350673A1
公开(公告)日：2018-12-06
申请号：US15927106
申请日：2018-03-21
Inventor： Pin-Hong Chen , Chih-Chieh Tsai , Tzu-Chieh Chen , Kai-Jiun Chang , Chia-Chen Wu , Yi-An Huang , Tsun-Min Cheng , Yi-Wei Chen , Wei-Hsin Liu
IPC: H01L21/768 , H01L21/324 , H01L23/532
Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.
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公开(公告)号：US20180301458A1
公开(公告)日：2018-10-18
申请号：US15922899
申请日：2018-03-15
Inventor： Pin-Hong Chen , Tsun-Min Cheng , Chih-Chieh Tsai , Tzu-Chieh Chen , Kai-Jiun Chang , Chia-Chen Wu , Yi-An Huang , Yi-Wei Chen , Hsin-Fu Huang , Chi-Mao Hsu , Li-Wei Feng , Ying-Chiao Wang , Chung-Yen Feng
IPC: H01L27/108 , H01L23/532 , H01L23/522 , H01L21/285 , H01L23/528 , H01L21/768
Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
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公开(公告)号：US10050146B2
公开(公告)日：2018-08-14
申请号：US14462114
申请日：2014-08-18
Applicant: United Microelectronics Corp.
Inventor： Man-Ling Lu , Yu-Hsiang Hung , Chung-Fu Chang , Yen-Liang Wu , Wen-Jiun Shen , Chia-Jong Liu , Ssu-I Fu , Yi-Wei Chen
IPC: H01L29/78 , H01L29/66 , H01L21/308
Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.
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公开(公告)号：US20180190488A1
公开(公告)日：2018-07-05
申请号：US15859750
申请日：2018-01-02
Inventor： Mei-Ling Chen , Wei-Hsin Liu , Yi-Wei Chen , Ching-Hsiang Chang , Jui-Min Lee , Chia-Lung Chang , Tzu-Chin Wu , Shih-Fang Tzou
IPC: H01L21/02
CPC classification number: H01L21/02532 , H01L21/02422 , H01L21/02592 , H01L21/0262 , H01L21/02664
Abstract: The present invention provides a method for forming an amorphous silicon multiple layer structure, the method comprises the flowing steps: first, a substrate material layer is provided, next, a first amorphous silicon layer is formed on the substrate material layer, wherein the first amorphous silicon layer includes a plurality of hydrogen atoms disposed therein, afterwards, an UV curing process is performed to the first amorphous silicon layer, so as to remove the hydrogen atoms from the first amorphous silicon layer, finally, a second amorphous silicon layer is formed on the first amorphous silicon layer.
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