中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

36 records (took 0.026 seconds)

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20160020323A1

    公开(公告)日：2016-01-21

    申请号：US14463676

    申请日：2014-08-20

    Applicant: United Microelectronics Corp.

    Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Wen-Jiun Shen ,  Ssu-I Fu ,  Man-Ling Lu ,  Chia-Jong Liu ,  Yi-Wei Chen

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7848 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7854

    Abstract: A semiconductor device includes a fin structure, an insulating structure, a protruding structure, an epitaxial structure, and a gate structure. The fin structure and the insulating structure are disposed on the substrate. The protruding structure is in direct contact with the substrate and partially protrudes from the insulating structure, and the protruding structure is the fin structure. The epitaxial structure is disposed on a top surface of the fin structure and completely covers the top surface of the fin structure. In addition, the epitaxial structure has a curved top surface. The gate structure covers the fin structure and the epitaxial structure.

    Abstract translation: 半导体器件包括鳍结构，绝缘结构，突出结构，外延结构和栅极结构。 翅片结构和绝缘结构设置在基板上。 突出结构与基板直接接触，并从绝缘结构部分突出，突出结构为翅片结构。 外延结构设置在翅片结构的顶表面上并完全覆盖翅片结构的顶表面。 此外，外延结构具有弯曲的顶表面。 栅极结构覆盖鳍结构和外延结构。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
    半导体器件及其形成方法

    公开(公告)号：US20160020110A1

    公开(公告)日：2016-01-21

    申请号：US14462114

    申请日：2014-08-18

    Applicant: United Microelectronics Corp.

    Inventor： Man-Ling Lu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Wen-Jiun Shen ,  Chia-Jong Liu ,  Ssu-I Fu ,  Yi-Wei Chen

    IPC: H01L21/308 ,  H01L29/78

    CPC classification number: H01L29/7848 ,  H01L21/3086 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78

    Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.

    Abstract translation: 提供一种形成半导体器件的方法。 在基板上设置至少一个层叠结构。 第一间隔物层，第二间隔物层和第三间隔物层依次形成在基板上并覆盖层叠结构。 第一，第二和第三间隔物材料层被蚀刻以在堆叠结构的侧壁上形成三层间隔结构。 三层间隔结构包括从层叠结构的一侧形成第一间隔物，第二间隔物和第三间隔物，第二间隔物的介电常数小于第一间隔物的介电常数和 第三间隔物的介电常数。

    Implantation processing step for a recess in finFET
    4.
    发明授权
    Implantation processing step for a recess in finFET 有权
    用于FinFET凹陷的植入处理步骤

    公开(公告)号：US09093477B1

    公开(公告)日：2015-07-28

    申请号：US14536674

    申请日：2014-11-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chien-Ting Lin ,  Chia-Jong Liu

    IPC: H01L21/425 ,  H01L29/66 ,  H01L21/265

    CPC classification number: H01L21/26586 ,  H01L21/2658 ,  H01L29/66795

    Abstract: An implantation processing step includes the following steps for a recess in a FinFET. At least a fin structure is formed on a substrate. A gate is formed across the fin structure. A recess is formed in the fin structure beside the gate. An angle anti-punch through implant is performed to form an embedded layer in the fin structure right below the gate. An angle barrier implant is performed to form a barrier liner in the fin structure surrounding the recess. A junction implant is performed to form a junction doped region in the fin structure below the recess.

    Abstract translation: 注入处理步骤包括FinFET中的凹部的以下步骤。 至少在基板上形成翅片结构。 跨鳍片结构形成栅极。 在闸门旁边的翅片结构中形成凹部。 执行角度抗冲穿植入物以在栅极正下方的翅片结构中形成嵌入层。 执行角度阻挡植入物以在围绕凹部的鳍结构中形成阻挡衬里。 执行结注入以在凹槽下方的翅片结构中形成结掺杂区。

    Semiconductor Structure
    7.
    发明申请
    Semiconductor Structure 有权
    半导体结构

    公开(公告)号：US20160163797A1

    公开(公告)日：2016-06-09

    申请号：US14594159

    申请日：2015-01-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jiun Shen ,  Chia-Jong Liu ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Man-Ling Lu ,  Yi-Wei Chen ,  Jhen-Cyuan Li

    IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78

    CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847

    Abstract: The present invention provides a semiconductor structure, comprising a substrate, a gate structure, a source/drain region and at least a dislocation. The gate structure is disposed on the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure. The dislocation is located in the source/drain region, and is asymmetrical relating to a middle axis of the source/drain region.

    Abstract translation: 本发明提供一种半导体结构，其包括衬底，栅极结构，源极/漏极区域和至少位错。 栅极结构设置在基板上。 源极/漏极区域在栅极结构的两侧设置在衬底中。 位错位于源极/漏极区域中，并且与源极/漏极区域的中间轴线不对称。

    FABRICATION METHOD OF SEMICONDUCTOR STRUCTURE
    9.
    发明申请
    FABRICATION METHOD OF SEMICONDUCTOR STRUCTURE 有权
    半导体结构的制造方法

    公开(公告)号：US20150364568A1

    公开(公告)日：2015-12-17

    申请号：US14341838

    申请日：2014-07-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Man-Ling Lu ,  Chia-Jong Liu ,  Wen-Jiun Shen ,  Yi-Wei Chen

    IPC: H01L29/66

    CPC classification number: H01L29/6656 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

    Abstract: A fabrication method of a semiconductor structure includes the following steps. First of all, a gate structure is provided on a substrate, and a first material layer is formed on the substrate and the gate structure. Next, boron dopant is implanted to the substrate, at two sides of the gate structure, to form a first doped region, and P type conductive dopant is implanted to the substrate, at the two sides of the gate structure, to form a second doped region. As following, a second material layer is formed on the first material layer. Finally, the second material layer, the first material layer and the substrate at the two sides of the gate structure are etched sequentially, and a recess is formed in the substrate, at the two sides of the gate structure, wherein the recess is positioned within the first doped region.

    Abstract translation: 半导体结构的制造方法包括以下步骤。 首先，在基板上设置栅极结构，在基板和栅极结构上形成第一材料层。 接下来，在栅极结构的两侧将硼掺杂剂注入到衬底中以形成第一掺杂区，并且在栅极结构的两侧将P型导电掺杂剂注入到衬底中，以形成第二掺杂区 地区。 如下，在第一材料层上形成第二材料层。 最后，栅极结构的两侧的第二材料层，第一材料层和衬底被顺序地蚀刻，并且在栅极结构的两侧在衬底中形成凹部，其中凹部位于 第一掺杂区域。

Patent Agency Ranking