公开(公告)号：KR1020110005079A

公开(公告)日：2011-01-17

申请号：KR1020090062606

申请日：2009-07-09

Applicant: 서울대학교산학협력단

Inventor： 박병국 ,  이정업

IPC: H01L29/06 ,  H01L29/775

Abstract: PURPOSE: A single electron transistor and a method for manufacturing the same are provided to form two quantum dots on one silicon pin by forming two side gates and control gates on a first gate insulating film along a channel. CONSTITUTION: A silicon layer(16a) includes a vertical pin shaped channel region on a buried oxide film of a silicon-on-insulator substrate(14). A first gate insulating film(62) forms at vertical pin side on the channel region. A first side gate(71) and a second side gate(72) are separately formed on the buried oxide film. A control gate(82) is formed on the buried oxide film. The side gates and the control gate are symmetrically formed at both sides of the channel region.

Abstract translation: 目的：提供单电子晶体管及其制造方法，通过沿通道在第一栅极绝缘膜上形成两个侧栅极和控制栅极，在一个硅芯上形成两个量子点。 构成：硅层（16a）包括在绝缘体上硅衬底（14）的掩埋氧化膜上的垂直引脚形沟道区。 第一栅极绝缘膜（62）在沟道区域的垂直销侧形成。 第一侧栅极（71）和第二侧栅极（72）分别形成在掩埋氧化膜上。 在掩埋氧化膜上形成控制栅极（82）。 侧栅极和控制栅对称地形成在沟道区域的两侧。

公开(公告)号：KR1020100042968A

公开(公告)日：2010-04-27

申请号：KR1020080102209

申请日：2008-10-17

Applicant: 서울대학교산학협력단

Inventor： 박병국 ,  윤장근 ,  박일한

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/1037 ,  H01L29/42376 ,  H01L29/42392

Abstract: PURPOSE: A semiconductor device with a stacked array structure and a manufacturing method thereof are provided to improve the control of each channel of a gate by surrounding each semiconductor layer with one gate. CONSTITUTION: A semiconductor layer is vertically separated from a substrate(100) and one or more semiconductor layer are stacked. A gate(510) passes through the semiconductor layer while interposing a gate insulation layer on each semiconductor layer. A source(222) and a drain(226) are formed on both sides of the gate on each semiconductor layer. An interlayer insulation layer(600) surrounds the source and drain of each semiconductor layer. The interlayer insulation layer is formed on an empty space around each semiconductor layer.

Abstract translation: 目的：提供具有堆叠阵列结构的半导体器件及其制造方法，以通过用一个栅极围绕每个半导体层来改善栅极的每个沟道的控制。 构成：半导体层与衬底（100）垂直分离，并且堆叠一个或多个半导体层。 栅极（510）穿过半导体层，同时在每个半导体层上插入栅极绝缘层。 源极（222）和漏极（226）形成在每个半导体层上的栅极的两侧。 层间绝缘层（600）围绕每个半导体层的源极和漏极。 层间绝缘层形成在每个半导体层周围的空的空间上。