Verification plans to merging design verification metrics
    159.
    发明授权
    Verification plans to merging design verification metrics 有权
    合并设计验证指标的验证计划

    公开(公告)号:US08413088B1

    公开(公告)日:2013-04-02

    申请号:US12426188

    申请日:2009-04-17

    CPC classification number: G06F17/5022 G01R31/2848 G06F17/504

    Abstract: A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment on the invention, a plurality of verification scopes of an integrated circuit design as defined as part of a verification plan. A plurality of verification runs are executed within two or more verification scopes defined by the verification plan. At least two verification runs are selected to merge verification results together. Like named scenarios are merged together for each verification scope to generate merged verification results that are then stored into a merge database. A verification report is generated for the integrated circuit design from the merged verification results. A merge point may be specified so like named subtrees and subgroups may be merged across different verification scopes of selected verification runs. The merge point may combine check and coverage results obtained during simulation with check and coverage results obtained during formal verification.

    Abstract translation: 提供了一种用于产生数字电路验证的方法和装置。 在本发明的示例性实施例中,定义为验证计划的一部分的集成电路设计的多个验证范围。 在由验证计划定义的两个或多个验证范围内执行多个验证运行。 选择至少两次验证运行以将验证结果合并在一起。 对于每个验证范围,像命名方案一样合并生成合并的验证结果,然后将其存储到合并数据库中。 从合并的验证结果生成集成电路设计的验证报告。 可以指定合并点,以便命名子树和子组可以在所选验证运行的不同验证范围之间合并。 合并点可以将在模拟期间获得的检查和覆盖结果与在正式验证期间获得的检查和覆盖结果相结合。

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