Handling an input/output store instruction

    公开(公告)号:AU2020213829A1

    公开(公告)日:2021-05-20

    申请号:AU2020213829

    申请日:2020-01-14

    Applicant: IBM

    Abstract: A data processing system (210) and a method for handling an input/output store instruction (30), comprising a system nest (18) communicatively coupled to at least one input/output bus (22) by an input/output bus controller (20). The data processing system (210) further comprises at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load from and/or store data to at least one external device (214) which is communicatively coupled to the input/output bus (22). The data processing unit (216) is configured to complete the input/output store instruction (30) before an execution of the input/output store instruction (30) in the system nest (18) is completed. The asynchronous core-nest interface (14) comprises an input/output status array (44) with multiple input/output status buffers (24).

    PROCESSOR ASSIST FACILITY
    153.
    发明专利

    公开(公告)号:CA2874184C

    公开(公告)日:2021-01-12

    申请号:CA2874184

    申请日:2012-11-26

    Applicant: IBM

    Abstract: An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken.

    Temporarily suppressing processing of a restrained storage operand request

    公开(公告)号:AU2018208453B2

    公开(公告)日:2020-10-22

    申请号:AU2018208453

    申请日:2018-01-09

    Applicant: IBM

    Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request. The processing unit performing the processing may proceed with processing of the restrained storage operand request, without performing the suppressing, where the processing can be accomplished using cache private to the processing unit. Otherwise the suppressing may continue until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.

    GENERIEREN UND ÜBERPRÜFEN VON ABLAUFVERFOLGUNGEN VON HARDWARE-ANWEISUNGEN EINSCHLIESSLICH DATENINHALTEN DES ARBEITSSPEICHERS

    公开(公告)号:DE112018001257T5

    公开(公告)日:2019-12-12

    申请号:DE112018001257

    申请日:2018-05-21

    Applicant: IBM

    Abstract: Ausführungen der vorliegenden Erfindung betreffen ein durch einen Computer umgesetztes Verfahren zum Generieren und Überprüfen von Ablaufverfolgungen von Hardware-Anweisungen, die Dateninhalte des Arbeitsspeichers enthalten. Das Verfahren enthält ein Initiieren einer Erfassung von speicherinternen Ablaufverfolgungs- (IMT) Daten für einen Prozessor, wobei die IMT-Daten eine Anweisungsablaufverfolgung sind und gesammelt werden, während Anweisungen eine Ausführungs-Pipeline des Prozessors durchlaufen. Das Verfahren enthält ferner ein Erfassen von Inhalten von architekturgebundenen Registern des Prozessors durch: ein Speichern der Inhalte der architekturgebundenen Register in einem vorbestimmten Arbeitsspeicher-Speicherplatz, und ein Veranlassen, dass eine Lade-Speicher-Einheit (LSU) Inhalte des vorbestimmten Arbeitsspeicher-Speicherplatzes liest.

Patent Agency Ranking