A VERTEX BASED GEOMETRY ENGINE SYSTEM FOR USE IN INTEGRATED CIRCUIT DESIGN
    162.
    发明公开
    A VERTEX BASED GEOMETRY ENGINE SYSTEM FOR USE IN INTEGRATED CIRCUIT DESIGN 失效
    顶点几何基于机器系统所使用的集成电路模型

    公开(公告)号:EP0979448A1

    公开(公告)日:2000-02-16

    申请号:EP97935017.0

    申请日:1997-07-21

    CPC classification number: G06F17/5081

    Abstract: A system for processing geometry which reduces the amount of memory spaces while improving the processing speed. The system delivers vertices in sequence to a vertex queue (70) so that data in the vertex queue is freed as it is delivered and only minimal intermediate results are stored. By this incremental evaluation, less memory space is needed. In another aspect of the invention the vertices are maintained in the proper sequence so that sorting operation can be eliminated. A sorted vertex queue (70) and an unsorted vertex list (72) are utilized so that resorting of the entire vertex list may be prevented. In addition, a compressed format (34) for storing geometry is utilized based on the fact that much information can be rederived from a sorted and reduced vertex queue.

    BiCMOS LOGIC CIRCUIT
    164.
    发明公开
    BiCMOS LOGIC CIRCUIT 失效
    BiCMOS逻辑电路。

    公开(公告)号:EP0628226A1

    公开(公告)日:1994-12-14

    申请号:EP93907156.0

    申请日:1993-02-23

    Abstract: Circuit logique BICMOS amélioré (70) utilisant une paire de transistors bipolaires (21, 22) à couplage par émetteurs pour comparer de manière différentielle un signal d'entrée (Vin) et un niveau de référence logique (VBIAS). Chaque transistor bipolaire est chargé de manière résistive par un réseau de transistors (26, 27) à semiconducteur à grille isolée par oxyde métallique à canal P (PMOS) couplés en parallèle. La grille d'au moins une des combinaisons parallèles de transistors est couplée à un signal de commande (VREF2) fournissant une résistance de charge variable. De préférence, le signal de commande est fourni par un réseau de retour (52, 53) servant à maintenir à une valeur constante l'excursion de tension constante dans le réseau, malgré les variations de température.

    BIPOLAR JUNCTION TRANSISTOR EXHIBITING IMPROVED BETA AND PUNCH-THROUGH CHARACTERISTICS
    165.
    发明公开
    BIPOLAR JUNCTION TRANSISTOR EXHIBITING IMPROVED BETA AND PUNCH-THROUGH CHARACTERISTICS 失效
    具有改进的STROMVERSTÄRKUNGS-和突破性的功能BOPOLARTRANSISTOR。

    公开(公告)号:EP0609351A1

    公开(公告)日:1994-08-10

    申请号:EP92922539.0

    申请日:1992-10-19

    Abstract: Transistor bipolaire possédant un émetteur (25), une base (31) et un collecteur (30). Il comprend une zone de base intrinsèque (33) à zones latérales étroites (p-) et à zone centrale plus large (37). Les zones latérales sont contiguës à la zone dopée (31), et la zone centrale (37) se trouve sous l'émetteur (25). Le profil de dopage latéral de la base est tel que les concentrations de dopage dans la zone dopée (31) et la zone centrale (37) sont relativement élevées par rapport à celles dans les zones latérales étroites (p-) de la base intrinsèque (33). L'association des zones latérales étroites (p-) au profil de dopage latéral de la base limite l'étendue de la zone de déplétion à l'intérieur de la base, ce qui assure une réduction de la tension de claquage du transistor sans entraîner une perte du gain en courant.

    SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS
    166.
    发明公开
    SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS 审中-公开
    系统维护工作人员培训

    公开(公告)号:EP3161616A2

    公开(公告)日:2017-05-03

    申请号:EP15815691.9

    申请日:2015-06-26

    Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.

    Abstract translation: 公开了可扩展的宽操作,其中在执行指令中使用比处理器和存储器之间的数据路径更宽的操作数。 可扩展的宽操作数减少了执行计算的功能单元的设计中相关处理器的特性的影响,包括寄存器文件的宽度,处理器时钟速率,处理器的异常子系统以及加载中的操作顺序 并在宽缓存中使用操作数。

    LOUDSPEAKER WITH IMPROVED DIRECTIONAL BEHAVIOR AND REDUCTION OF ACOUSTICAL INTERFERENCE
    167.
    发明公开
    LOUDSPEAKER WITH IMPROVED DIRECTIONAL BEHAVIOR AND REDUCTION OF ACOUSTICAL INTERFERENCE 审中-公开
    具有改进的定向行为喇叭及抑制弹性干扰

    公开(公告)号:EP3041265A3

    公开(公告)日:2016-07-20

    申请号:EP15183015.5

    申请日:2015-08-28

    Abstract: Loudspeaker systems and assemblies are provided in which mid-frequency producing drivers (20, 20') are provided on opposing sides of a high frequency source comprising a linear high-frequency source (10) connected to a waveguide (40). Crossover circuitry is provided such that the acoustic output from the mid-frequency drivers (20, 20') overlaps with that of the high-frequency source (10) over an intermediate frequency range associated with acoustic interference between the mid-frequency producing drivers (20, 20'). In some embodiments, the mid-frequency producing drivers (20, 20') are recessed behind the output of the waveguide (40), and optionally angled outwardly from the waveguide (40), in order decrease the distance therebetween.

    Abstract translation: 在哪个中频驱动生产(20,20“)设置在相对的高频源的侧面包括连接到一个波导(40)的线性高频源(10)提供的扬声器系统和组件。 交叉电路配备检查的确从中频驱动器(20,20“)的声输出重叠,没有与中间频率产生驱动器之间的声学​​干涉相关联的中间频率范围中的高频源(10)上的( 20,20“)。 在一些实施例中,中频驱动生产(20,20“)的凹入的波导(40)的输出端的后面,并任选地从所述波导(40)向外倾斜,为了减小距离有之间。

    LOUDSPEAKER WITH IMPROVED DIRECTIONAL BEHAVIOR AND REDUCTION OF ACOUSTICAL INTERFERENCE
    168.
    发明公开
    LOUDSPEAKER WITH IMPROVED DIRECTIONAL BEHAVIOR AND REDUCTION OF ACOUSTICAL INTERFERENCE 审中-公开
    扬声器具有改善的方向性和减少声学干扰

    公开(公告)号:EP3041265A2

    公开(公告)日:2016-07-06

    申请号:EP15183015.5

    申请日:2015-08-28

    Abstract: Loudspeaker systems and assemblies are provided in which mid-frequency producing drivers (20, 20') are provided on opposing sides of a high frequency source comprising a linear high-frequency source (10) connected to a waveguide (40). Crossover circuitry is provided such that the acoustic output from the mid-frequency drivers (20, 20') overlaps with that of the high-frequency source (10) over an intermediate frequency range associated with acoustic interference between the mid-frequency producing drivers (20, 20'). In some embodiments, the mid-frequency producing drivers (20, 20') are recessed behind the output of the waveguide (40), and optionally angled outwardly from the waveguide (40), in order decrease the distance therebetween.

    Abstract translation: 提供扬声器系统和组件,其中中频产生驱动器(20,20')设置在包括连接到波导(40)的线性高频源(10)的高频源的相对侧上。 提供交叉电路,使得来自中频驱动器(20,20')的声输出在与中频产生驱动器(20,20')之间的声干涉相关的中频范围上与高频源(10)的声输出重叠 20,20')。 在一些实施例中,中频产生驱动器(20,20')凹入波导(40)的输出后面,并且可选地从波导(40)向外倾斜,以便减小它们之间的距离。

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