Abstract:
A system for processing geometry which reduces the amount of memory spaces while improving the processing speed. The system delivers vertices in sequence to a vertex queue (70) so that data in the vertex queue is freed as it is delivered and only minimal intermediate results are stored. By this incremental evaluation, less memory space is needed. In another aspect of the invention the vertices are maintained in the proper sequence so that sorting operation can be eliminated. A sorted vertex queue (70) and an unsorted vertex list (72) are utilized so that resorting of the entire vertex list may be prevented. In addition, a compressed format (34) for storing geometry is utilized based on the fact that much information can be rederived from a sorted and reduced vertex queue.
Abstract:
A jet engine test cell capable of dissipating infrasound includes an engine test section (18), an augmentor (24) and an exhaust stack (28) having a structure (33) near its open end (31) for dissipating infrasound.
Abstract:
Circuit logique BICMOS amélioré (70) utilisant une paire de transistors bipolaires (21, 22) à couplage par émetteurs pour comparer de manière différentielle un signal d'entrée (Vin) et un niveau de référence logique (VBIAS). Chaque transistor bipolaire est chargé de manière résistive par un réseau de transistors (26, 27) à semiconducteur à grille isolée par oxyde métallique à canal P (PMOS) couplés en parallèle. La grille d'au moins une des combinaisons parallèles de transistors est couplée à un signal de commande (VREF2) fournissant une résistance de charge variable. De préférence, le signal de commande est fourni par un réseau de retour (52, 53) servant à maintenir à une valeur constante l'excursion de tension constante dans le réseau, malgré les variations de température.
Abstract:
Transistor bipolaire possédant un émetteur (25), une base (31) et un collecteur (30). Il comprend une zone de base intrinsèque (33) à zones latérales étroites (p-) et à zone centrale plus large (37). Les zones latérales sont contiguës à la zone dopée (31), et la zone centrale (37) se trouve sous l'émetteur (25). Le profil de dopage latéral de la base est tel que les concentrations de dopage dans la zone dopée (31) et la zone centrale (37) sont relativement élevées par rapport à celles dans les zones latérales étroites (p-) de la base intrinsèque (33). L'association des zones latérales étroites (p-) au profil de dopage latéral de la base limite l'étendue de la zone de déplétion à l'intérieur de la base, ce qui assure une réduction de la tension de claquage du transistor sans entraîner une perte du gain en courant.
Abstract:
Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.
Abstract:
Loudspeaker systems and assemblies are provided in which mid-frequency producing drivers (20, 20') are provided on opposing sides of a high frequency source comprising a linear high-frequency source (10) connected to a waveguide (40). Crossover circuitry is provided such that the acoustic output from the mid-frequency drivers (20, 20') overlaps with that of the high-frequency source (10) over an intermediate frequency range associated with acoustic interference between the mid-frequency producing drivers (20, 20'). In some embodiments, the mid-frequency producing drivers (20, 20') are recessed behind the output of the waveguide (40), and optionally angled outwardly from the waveguide (40), in order decrease the distance therebetween.
Abstract:
Loudspeaker systems and assemblies are provided in which mid-frequency producing drivers (20, 20') are provided on opposing sides of a high frequency source comprising a linear high-frequency source (10) connected to a waveguide (40). Crossover circuitry is provided such that the acoustic output from the mid-frequency drivers (20, 20') overlaps with that of the high-frequency source (10) over an intermediate frequency range associated with acoustic interference between the mid-frequency producing drivers (20, 20'). In some embodiments, the mid-frequency producing drivers (20, 20') are recessed behind the output of the waveguide (40), and optionally angled outwardly from the waveguide (40), in order decrease the distance therebetween.
Abstract:
A matrix or array of elongated tubular members, each member being formed by spirally winding a piece or pieces of material into a generally cylindrical shape, wherein the matrix or array is mounted in an airflow to reduce the noise associated with and/or produced by the airflow.
Abstract:
A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.