公开(公告)号：WO1996015554A1

公开(公告)日：1996-05-23

申请号：PCT/US1995014602

申请日：1995-11-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BUI, Nguyen, Duc

IPC: H01L23/485

CPC classification number: H01L24/05 ,  H01L21/32137 ,  H01L2224/02166 ,  H01L2224/05073 ,  H01L2224/05599 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/00014

Abstract: An improved transistor design and methods of construction and testing for same. The novel transistor design method includes the steps of providing a transistor (10') with multiple common gate areas; connecting each gate area to a pad; and adjusting the ratio of the area of the pad to the total of the gate areas to provide a predetermined ratio. The ratio may be adjusted by adjusting the size of the gate, in a single gate implementation, or adjusting the number of gates in a multiple gate configuration. The novel transistor includes a substrate (12'), at least one source (26') disposed on the substrate; at least one drain (28') disposed on the substrate; and at least one gate (30') disposed on the substrate between the source and the drain. The gate has a first layer of at least partially conductive material of area Ag connected to a pad (34') of area Ap. In accordance with the present teachings, the antenna ratio R of the area of the pad Ap to the area of the gate Ag is a predetermined number. In practice, the ratio R would be chosen to be a minimum so that deleterious plasma currents attracted to the gate area would be reduced. In a particular implementation, the transistor includes plural gates each having a layer of at least partially conductive material of area Agn where n is any integer between 1 and N and where N is the total number of gates. In this case, the plural gates are interconnected and the ratio R is a predetermined number equal to Ap/Agtotal, where Agtotal is the sum of the areas Agn and n is any integer between 1 and N. The novel method for testing multiple gate transistors includes the steps of connecting a first terminal of each of said transistors to a ground; interconnecting a second terminal of each transistor and applying a first source of supply potential; and selectively applying a second source of supply potential to a third terminal of a selected transistor.

Abstract translation: 改进的晶体管设计及其构造和测试方法相同。 新颖的晶体管设计方法包括以下步骤：提供具有多个公共栅极区域的晶体管（10'）; 将每个门区连接到垫; 并且调整焊盘的面积与栅极区域的总和的比率以提供预定的比率。 可以通过在单个栅极实现中调整栅极的尺寸或者调整多栅极配置中的栅极的数量来调节该比率。 新型晶体管包括衬底（12'），设置在衬底上的至少一个源极（26'）; 设置在所述基板上的至少一个漏极（28'）; 以及设置在源极和漏极之间的衬底上的至少一个栅极（30'）。 栅极具有连接到区域Ap的焊盘（34'）的区域Ag的至少部分导电材料的第一层。 根据本教导，焊盘Ap的面积与栅极Ag的面积的天线比率R是预定数量。 在实践中，比率R将被选择为最小值，使得吸引到栅极区域的有害等离子体电流将被减小。 在具体实施方式中，晶体管包括多个栅极，每个栅极具有区域Agn的至少部分导电材料的层，其中n是1和N之间的任何整数，其中N是门的总数。 在这种情况下，多个栅极互连，比率R是等于Ap / Agtotal的预定数量，其中Agtotal是区域Agn之和，n是1与N之间的任何整数。用于测试多个栅极晶体管的新颖方法 包括将每个所述晶体管的第一端子连接到地的步骤; 互连每个晶体管的第二端子并施加第一电源电位; 以及选择性地将第二电源电位施加到所选晶体管的第三端。

公开(公告)号：WO1996011475A1

公开(公告)日：1996-04-18

申请号：PCT/US1995013012

申请日：1995-09-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  TANG, Yuan ,  CHANG, Chi ,  VAN BUSKIRK, Michael, A. ,  CHANG, Chung, K.

IPC: G11C16/06

CPC classification number: G11C16/14

Abstract: There is provided an improved method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices. A relatively low positive pulse voltage is applied to a source region of the EEPROM devices during an entire erase cycle. Simultaneously, a negative ramp voltage is applied to a control gate of the EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle.

Abstract translation: 提供了一种用于消除快速EEPROM装置的隧道氧化物中的循环诱导电子捕获的改进方法。 在整个擦除周期期间，相对较低的正脉冲电压被施加到EEPROM器件的源极区域。 同时，在整个擦除周期期间，向EEPROM器件的控制栅极施加负斜坡电压，从而实现从擦除周期开始到擦除周期结束的平均隧道场。

公开(公告)号：WO1988002204A1

公开(公告)日：1988-03-24

申请号：PCT/US1987002370

申请日：1987-09-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LUNDERIUS, Erik ,  JOHANSSON, Jan

IPC: H04M01/00

CPC classification number: H04M19/08

Abstract: A subscriber power controller (7), which regulates a voltage supply for an Integrated Services Digital Network (ISDN). The power controller and the ISDN must be protected from low input voltage and low input power. The invention provides low voltage and low power detection circuits as part of the power controller. A low voltage detection circuit (12) which generates a first detection signal is formed of a comparator with hysteresis (24, Fig. 3) and an ECL output stage (26, Fig. 3). A low power detection circuit (22) which provides a second detection signal is formed of a comparator with hysteresis (43, Fig. 4) and an output stage (44, Fig. 4). The first detection signal is used to disable the power controller and the second detection signal is used to disable high power functions of the ISDN.

Abstract translation: 一种用于调节综合业务数字网（ISDN）的电压供应的用户功率控制器（7）。 电源控制器和ISDN必须防止低输入电压和低输入功率。 本发明提供作为功率控制器的一部分的低电压和低功率检测电路。 产生第一检测信号的低电压检测电路（12）由具有滞后的比较器（图3中的24）和ECL输出级（图3中的26）形成。 提供第二检测信号的低功率检测电路（22）由具有滞后的比较器（图4中的43）和输出级（图4中的44）形成。 第一个检测信号用于禁用功率控制器，第二个检测信号用于禁用ISDN的高功率功能。

公开(公告)号：WO1988001109A1

公开(公告)日：1988-02-11

申请号：PCT/US1987001925

申请日：1987-08-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  JOHANSSON, Jan ,  CHEN, Shallop, J.

IPC: H02H03/24

CPC classification number: H04M19/08 ,  G06F1/12 ,  G06F1/24

Abstract: A reset and synchronization interface circuit (10) for use in a subscriber power controller (7) includes a reset circuit portion (12) and a synchronization circuit portion (14). The reset circuit portion is formed of a first comparator (16), a second comparator (18), and an output network (20) for generating a reset signal. The first comparator compares an input signal with the reference voltage to produce a first output signal and a second output signal. The second comparator compares the first output signal from the first comparator with the reference voltage to produce a third output signal. The output network inverts and shifts the level of the third output signal to produce the reset signal. The synchronization circuit portion is formed of a third comparator (22) and an AND logic gate (24) for generating a modified synchronizing signal. The third comparator inverts a synchronizing clock signal to generate a complementary synchronizing clock signal. The AND logic gate combines logically the second output signal from the first comparator with the complementary synchronizing clock signal to produce the modified synchronizing signal.

公开(公告)号：WO1985004062A1

公开(公告)日：1985-09-12

申请号：PCT/US1985000308

申请日：1985-02-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  VARADARAJAN, Hemmige, D.

IPC: H03K19/086

CPC classification number: H03K19/0823 ,  H03K19/0866

Abstract: Three-level ECL or four-level CML are feasible when a low drop current source (34) is incorporated in the series-gated arrangement. The low drop current source (34) consumes less than one-tenth of the voltage span between VCC and ground. A greater portion of the voltage span between Vcc and ground, up to 4 volts, is therefore reserved for the three ECL levels or four CML levels of logic. Conventional power supplies are utilized yet the number of logic functions is increased.

公开(公告)号：WO1985003162A1

公开(公告)日：1985-07-18

申请号：PCT/US1984002107

申请日：1984-12-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  RINERSON, Darrell

IPC: G11C11/40

CPC classification number: H01L29/7883 ,  G11C16/0441 ,  H01L27/115

Abstract: A five volt only E2 PROM cell including metal bit read (12) and bit ground column (16) lines and polysilicon word select (50) and program row (54) lines. An interconnected word select and stacked gate transistor (52) serially connect the bit read and bit ground lines. The cell also includes a tunneling structure (24), disposed below the program row line (54), for charging or uncharging a floating polysilicon gate in the stacked gate transistor. The bit ground line (16) is disconnected from ground during the charging and uncharging operations.

公开(公告)号：WO1985002930A1

公开(公告)日：1985-07-04

申请号：PCT/US1984002125

申请日：1984-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SFARTI, Adrian ,  DINES, Steven

IPC: G09G01/24

CPC classification number: G09G5/393 ,  G09G5/222 ,  G09G5/24 ,  G09G5/243 ,  G09G5/363

Abstract: An apparatus and a method for character and graphics pattern generation in a bit mapped graphics display system that includes a pixel data manager (14) for supplying character bit maps and graphics patterns to a visible display memory (22). A character information memory (24) is utilized for the storage of character descriptive information which includes an address table (26), macro-instructions (28), (30), and (32) and character bit maps (34), (36) and (38). Each character in a set of characters has an associated macro-instruction and character bit map. The address table contains memory addresses that point to the macro-instructions. Each macro-instruction contains executable instructions that establish the size and location of a corresponding character bit map. To supply a character to the visible display memory, the pixel data manager fetches and executes a corresponding macro-instruction. Overhead burden on the central processing unit is minimized.

公开(公告)号：WO1985002472A1

公开(公告)日：1985-06-06

申请号：PCT/US1984001869

申请日：1984-11-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  YANG, Tsen-Shau

IPC: G05F03/16

CPC classification number: G05F3/30 ,  Y10S323/907

Abstract: A bandgap reference voltage generator includes compensation circuitry (33-37, 43-44 and 46) that renders the performance of the bandgap reference voltage generator independent of the static value of the supply voltage (Vcc) by providing a constant current through the self-regulating loop in the generator. The compensation circuitry (33-37, 43-44 and 46) effectively provides compensating terms for each Vcc-dependent term in the network equation that describes the operation of the bandgap reference voltage generator. In a preferred embodiment, the compensating terms also serve to make the operation of the bandgap voltage generator independent of temperature.

公开(公告)号：WO1985002307A1

公开(公告)日：1985-05-23

申请号：PCT/US1984001745

申请日：1984-10-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  THOMPSON, Michael, D. ,  MAZUMDER, Nikhil, C.

IPC: H03K19/088

CPC classification number: H03K19/01806 ,  H03K19/00353

Abstract: An improved logic level translator circuit for translating non-TTL circuits (82) to logic signals of TTL circuits (128). The translator circuit as presented includes circuitry (52 and 72) for providing elimination of noise spiking and the resultant erroneous switching caused by simultaneous conduction of TTL circuit outputs (60) as they change states.

公开(公告)号：WO1985001173A1

公开(公告)日：1985-03-14

申请号：PCT/US1984001329

申请日：1984-08-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  RALLAPALLI, Krishna ,  KAKU, Shinkyo

IPC: H04N01/40

CPC classification number: H04N1/4175 ,  G06T9/005

Abstract: A method and device for decoding two-dimensionally encoded digital facsimile signals. The method includes (a) accumulating the run lengths of color change picture elements in the reference line, (b) decoding a codeword to generate a displacement value, (c) combining the accumulated run length of a reference line color change picture element and a displacement value to obtain accumulated run lengths of coding line color change picture elements, and (d) determining the difference between accumulated run lengths of a coding line color change picture element. The difference is the decoded data. The device has a control logic (70), a reference line processing unit (80) for generating the accumulated run lengths of color change picture elements in the reference line, a coding line processing unit (81) for generating displacement values from the encoded codewords, and a first combining unit part (82) and second combining unit part (83) for combining the reference line accumulated run lengths and the displacement values to obtain the accumulated run lengths of color change picture elements in the coding line and for determining the differences between coding lines accumulated run lengths, which are the decoded run lengths of the color units in the coding line, respectively.