公开(公告)号：US20160240540A1

公开(公告)日：2016-08-18

申请号：US14620212

申请日：2015-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L27/11 ,  H01L29/06 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L27/3223 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor structure is provided, including a substrate, a plurality of first semiconductor devices, a plurality of second semiconductor devices, and a plurality of dummy slot contacts. The substrate has a device region, wherein the device region includes a first functional region and a second functional region, and a dummy region is disposed therebetween. The first semiconductor devices and a plurality of first slot contacts are disposed in the first functional region. The second semiconductor devices and a plurality of second slot contacts are disposed in the second functional region. The dummy slot contacts are disposed in the dummy region.

Abstract translation: 提供一种半导体结构，包括基板，多个第一半导体器件，多个第二半导体器件和多个虚拟插槽触点。 衬底具有器件区域，其中器件区域包括第一功能区域和第二功能区域，并且虚设区域设置在其间。 第一半导体器件和多个第一时隙触点设置在第一功能区域中。 第二半导体器件和多个第二槽触点设置在第二功能区域中。 虚拟插槽触点设置在虚拟区域中。

公开(公告)号：US09401358B1

公开(公告)日：2016-07-26

申请号：US14611843

申请日：2015-02-02

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L29/00 ,  H01L27/08 ,  H01L27/06

CPC classification number: H01L27/0802 ,  H01L27/0629 ,  H01L27/0647 ,  H01L28/20

Abstract: A semiconductor device structure having at least one thin-film resistor structure is provided. Through the metal plug(s) or metal wirings located on different layers, a plurality of stripe segments of the thin-film resistor structure is electrically connected to ensure the thin-film resistor structure with the predetermined resistance and less averting areas in the layout design.

Abstract translation: 提供具有至少一个薄膜电阻器结构的半导体器件结构。 通过位于不同层上的金属插头或金属布线，薄膜电阻器结构的多个条形段电连接，以确保具有预定电阻的薄膜电阻器结构和布局设计中较少的避免区域 。

公开(公告)号：US09349639B2

公开(公告)日：2016-05-24

申请号：US14510100

申请日：2014-10-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L23/485 ,  H01L21/76897 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing contact structure includes the steps of: providing a substrate having the semiconductor device and an interlayer dielectric thereon, wherein the semiconductor device includes a gate structure and a source/drain region; forming a patterned mask layer with a stripe hole on the substrate, and concurrently forming a stripe-shaped mask layer on the substrate; forming a patterned photoresist layer with a plurality of slot holes on the substrate, wherein at least one of the slot holes is disposed right above the source/drain region; and forming a contact hole in the interlayer dielectric by using the patterned mask layer, the stripe-shaped mask layer and the patterned photoresist layer as an etch mask, and the source/drain region is exposed from the bottom of the contact hole when the step of forming the contact hole is completed.

Abstract translation: 制造接触结构的方法包括以下步骤：提供其上具有半导体器件和层间电介质的衬底，其中所述半导体器件包括栅极结构和源极/漏极区; 在基板上形成具有条纹孔的图案化掩模层，并且在基板上同时形成条形掩模层; 在所述基板上形成具有多个槽孔的图案化光致抗蚀剂层，其中所述槽孔中的至少一个设置在所述源极/漏极区域正上方; 并且通过使用图案化掩模层，条形掩模层和图案化光致抗蚀剂层作为蚀刻掩模在层间电介质中形成接触孔，并且当步骤 形成接触孔。

公开(公告)号：US20160104646A1

公开(公告)日：2016-04-14

申请号：US14514374

申请日：2014-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Tsung-Hung Chang ,  Jia-Rong Wu ,  Ching-Ling Lin ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823431

Abstract: A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure, next, a hard mask layer and a first photoresist layer are formed on the fin structure, an first etching process is then performed on the first photoresist layer, afterwards, a plurality of patterned photoresist layers are formed on the remaining first photoresist layer and the remaining hard mask layer, where each patterned photoresist layer is disposed right above each gate structure, and the width of each patterned photoresist is larger than the width of each gate structure, and the patterned photoresist layer is used as a hard mask to perform an second etching process to form a plurality of second trenches.

Abstract translation: 一种半导体器件的制造方法，其特征在于，首先，在基板上形成有基板，在所述散热片结构上形成有多个栅极结构，然后将硬掩模层和第一光致抗蚀剂层 形成在鳍结构上，然后在第一光致抗蚀剂层上进行第一蚀刻工艺，然后在剩余的第一光致抗蚀剂层和剩余的硬掩模层上形成多个图案化的光致抗蚀剂层，其中每个图案化的光致抗蚀剂层被设置 每个栅极结构的正上方，并且每个图案化的光致抗蚀剂的宽度大于每个栅极结构的宽度，并且图案化的光致抗蚀剂层用作硬掩模以执行第二蚀刻工艺以形成多个第二沟槽。

公开(公告)号：US09306032B2

公开(公告)日：2016-04-05

申请号：US14062909

申请日：2013-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Chien-Ting Lin

IPC: H01L21/3205 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供了至少具有嵌入在其上形成绝缘材料的晶体管的衬底。 晶体管包括金属栅极。 接下来，进行蚀刻处理以去除金属栅极的一部分以形成凹部并且去除绝缘材料的一部分以形成锥形部分。 在形成凹部和绝缘材料的锥形部分之后，在基板上形成硬掩模层以填充凹部。 随后，硬掩模层被平坦化。

公开(公告)号：US09263392B1

公开(公告)日：2016-02-16

申请号：US14529129

申请日：2014-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Yi-Wei Chen

IPC: H01L21/336 ,  H01L23/535 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/0217 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal gate thereon and an interlayer dielectric (ILD) layer around the metal gate; removing part of the metal gate to form a recess; and depositing a mask layer in the recess and on the ILD layer while forming a void in the recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有金属栅极的基板和围绕金属栅极的层间电介质（ILD）层; 去除所述金属浇口的一部分以形成凹部; 以及在所述凹部中和所述ILD层上沉积掩模层，同时在所述凹部中形成空隙。

公开(公告)号：US20150179457A1

公开(公告)日：2015-06-25

申请号：US14639134

申请日：2015-03-05

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Shih-Fang Tzou

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/28079 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, and a bottom surface of the patterned mask layer is level with a top surface of the first interlayer dielectric. A spacer is then formed on each sidewall of the gate electrode. Subsequently, a second interlayer dielectric is formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 首先，在基板上形成第一层间电介质。 然后，在基板上形成栅电极，使得栅电极的周围被第一层间电介质包围。 之后，在栅电极上形成图案化掩模层，并且图案化掩模层的底表面与第一层间电介质的顶表面平齐。 然后在栅电极的每个侧壁上形成间隔物。 随后，形成第二层间电介质以覆盖图案化掩模层的顶表面和每个侧表面。 最后，在第一层间电介质和第二层间电介质中形成自对准接触结构。

公开(公告)号：US20150118836A1

公开(公告)日：2015-04-30

申请号：US14064722

申请日：2013-10-28

Applicant: United Microelectronics Corp.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Jia-Rong Wu ,  Ching-Wen Hung ,  Po-Chao Tsao

IPC: H01L29/66 ,  H01L21/768

CPC classification number: H01L29/66545 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is disclosed. Provided is a substrate having a dummy gate formed thereon, a spacer on a sidewall of the dummy gate and a first dielectric layer surrounding the spacer. The dummy gate is removed to form a gate trench. A gate dielectric layer and at least one work function layer is formed in the gate trench. The work function layer and the gate dielectric layer are pulled down, and a portion of the spacer is laterally removed at the same time to widen a top portion of the gate trench. A low-resistivity metal layer is formed in a bottom portion of the gate trench. A hard mask layer is formed in the widened top portion of the gate trench.

Abstract translation: 公开了制造半导体器件的方法。 提供了一种其上形成有虚拟栅极的基板，在虚拟栅极的侧壁上的间隔物和围绕间隔物的第一介电层。 去除伪栅极以形成栅极沟槽。 栅极介电层和至少一个功函数层形成在栅极沟槽中。 功函数层和栅介质层被下拉，并且间隔件的一部分同时被横向去除，以加宽栅沟槽的顶部。 在栅极沟槽的底部形成低电阻率金属层。 在栅沟槽的加宽的顶部形成有硬掩模层。

公开(公告)号：US20150118835A1

公开(公告)日：2015-04-30

申请号：US14062909

申请日：2013-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Chien-Ting Lin

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供了至少具有嵌入在其上形成绝缘材料的晶体管的衬底。 晶体管包括金属栅极。 接下来，进行蚀刻处理以去除金属栅极的一部分以形成凹部并且去除绝缘材料的一部分以形成锥形部分。 在形成凹部和绝缘材料的锥形部分之后，在基板上形成硬掩模层以填充凹部。 随后，硬掩模层被平坦化。

公开(公告)号：US20150008524A1

公开(公告)日：2015-01-08

申请号：US13933141

申请日：2013-07-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/11807

Abstract: An integrated circuit device structure, in which, a diffusion region is formed in a substrate, an extension conductor structure is contacted with the diffusion region and extended externally to a position along a surface of the substrate, the position is outside the diffusion region, another extension conductor structure is contacted with the diffusion region, a jumper conductor structure is disposed over the substrate and on these two extension conductor structures for electrically connecting these two extension conductor structures, the jumper conductor structure may be over one or more gate structures, a contact structure penetrates through a dielectric layer to be contacted with the jumper conductor structure, and a metal conductor line is contacted with the contact structure.

Abstract translation: 一种集成电路器件结构，其中在衬底中形成扩散区域，延伸导体结构与扩散区域接触并且在外部延伸到沿着衬底表面的位置，该位置在扩散区域外部，另一个 延伸导体结构与扩散区域接触，跳线导体结构设置在基板上方，并且在这两个延伸导体结构上用于电连接这两个延伸导体结构，跳线导体结构可以在一个或多个栅结构上，触点 结构穿透介电层以与跳线导体结构接触，并且金属导体线与接触结构接触。