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公开(公告)号：EP4141677A1
公开(公告)日：2023-03-01
申请号：EP22192295.8
申请日：2022-08-26
Inventor： SHARMA, Vivek Mohan , COLOMBO, Roberto
Abstract: A processing system is described. The processing system comprises an error detection circuit (46) configured to receive data bits (DATA) and ECC bits. The error detection circuit (46) calculates further ECC bits as a function of the data bits (DATA) and generates a syndrome (SYN) by comparing the calculated ECC bits with the received ECC bits. When the syndrome (SYN) corresponds to one of N + K single bit-flip reference syndromes, the error detection circuit (46) asserts a first error signal (ERR 1 ), and asserts one bit of a bit-flip signature (SIG) corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.
The processing system further comprises a test circuit (48) configured to provide, during a test-mode (TM), a sequence of patterns (PAT) to the error detection circuit (46), each pattern (PAT) comprising data bits (DATA) and ECC bits. Specifically, the test circuit (48) obtains a first pattern (PAT) without ECC errors, provides the first pattern (PAT) to the error detection circuit (46) and verifies whether the first error signal (ERR 1 ) is de-asserted and all bits of the bit-flip signature (SIG) are de-asserted. Moreover, the test circuit (48) obtains a sequence of N + K further bit-flip signatures (FSIG), each further bit-flip signature (SIG) having asserted a single bit. Moreover, the test circuit obtains (1008, 1014) for each further bit-flip signature (FSIG) a respective second pattern (PAT), wherein each second pattern (PAT) corresponds to a pattern having a single bit flipped with respect to a reference pattern at the positions of the single asserted bit of the respective further bit-flip signature (FSIG). The test circuit provides each second pattern (PAT) to the error detection circuit (46) and verifies whether the first error signal (ERR 1 ) is asserted and the bit-flip signature (SIG) corresponds to the respective further bit-flip signature.-
公开(公告)号：EP4105785A1
公开(公告)日：2022-12-21
申请号：EP22176130.7
申请日：2022-05-30
Inventor： CAVALLARO, Giuseppe , RENNIG, Fred
Abstract: A microcontroller (80) comprises a processing unit and a deserial-serial peripheral interface module (81'). The deserial-serial peripheral interface module is configured to be coupled to a communication bus (84) which operates according to a selected communication protocol. The processing unit is configured to read user data intended for inclusion in an outgoing frame encoded according to the selected communication protocol. The processing unit is further configured to calculate, as a function of the user data, a CRC value intended for inclusion in the outgoing frame. The processing unit is further configured to compose the outgoing frame including the user data and the calculated CRC value into the outgoing frame. The processing unit is further configured to produce a DSPI frame encoded according to the selected communication protocol as a function of the outgoing frame. The processing unit is further configured to program a data register of the deserial-serial peripheral interface module (81') with the DSPI frame. Operation of the deserial-serial peripheral interface module (81') results in transmission of the DSPI frame via the communication bus (84).
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公开(公告)号：EP4068101A1
公开(公告)日：2022-10-05
申请号：EP22163832.3
申请日：2022-03-23
Inventor： COLOMBO, Roberto , SHARMA, Vivek Mohan
IPC: G06F11/27 , G06F11/25 , G06F11/30 , G01R31/317 , G06F11/22
Abstract: A processing system (10a) is described. The processing system comprises a plurality of safety monitoring circuits (SM) configured to generate a plurality of error signals (ERR; ERR') by monitoring the operation of a processing core (102), a memory controller (100) and/or a resource (106). A fault collection and error management circuit (1206) receives the plurality of error signals (ERR; ERR') and generates one or more reaction signals.
In particular, the processing system comprises also a hardware connectivity test circuit (1208, 1210) configured to test the connectivity between the plurality of safety monitoring circuits (SM) and the fault collection and error management circuit (1206). The connectivity test circuit (1208, 1210) comprises for each error signal (ERR') a circuit (1208, SL, CL) configured to selectively assert or de-assert the respective error signal (ERR') generated by a respective safety monitoring circuit (SM) as a function of a respective selection signal (SE, CE). A control circuit (1210) sets the selection signals (SE, CE) in order to de-assert a first subset of the error signals (ERR') via the circuit (1208, SL, CL) and determines whether the respective error signals (ERR') of the first subset received by the fault collection and error management circuit (1206) are de-asserted. Similarly, the control circuit (1210) sets the selection signals (SE, CE) in order to assert a second subset of the error signals (ERR') via the circuit (1208, SL, CL) and determines whether the respective error signals (ERR') of the second subset received by the fault collection and error management circuit (1206) are asserted.-
公开(公告)号：EP4064794A2
公开(公告)日：2022-09-28
申请号：EP22305278.8
申请日：2022-03-11
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS , STMicroelectronics S.r.l. , STMicroelectronics Application GmbH
Inventor： GAERTNER, Manuel , SIRITO-OLIVIER, Philippe , TORRISI, Giovanni Luca , URBITSCH, Thomas , ROUSSEL, Christophe , BURKHARDT, Fritz
IPC: H05B45/37 , H05B45/325 , H05B45/10 , H05B45/46 , H05B45/52 , H05B47/25 , H02M3/335 , B60Q11/00 , B60Q1/14
Abstract: A system (100') comprises a microcontroller unit (102) and a driver device (101) coupled (105) to the microcontroller unit (102) to receive data therefrom. The driver device (101) comprises a plurality of output supply pins (101C 1 , ..., 101C n ) and is configured to selectively propagate (30 1 , ..., 30 n ) a supply voltage ( V BAT ) to the output supply pins (101C 1 , ..., 101C n ) to provide respective pulse-width modulated supply signals ( V BAT,1 , ..., V BAT,n ) at the output supply pins (101C 1 , ..., 101C n ). The driver device (101) is configured to compute respective duty-cycle values of the pulse-width modulated supply signals ( V BAT,1 , ..., V BAT,n ) as a function of the data received from the microcontroller unit (102) . The system further comprises a plurality of lighting devices (31 1,1 , ..., 31 1,m , 31 n ) coupled to the plurality of output supply pins (101C 1 , ..., 101C n ). The plurality of lighting devices (31 1,1 , ..., 31 1,m , 31 n ) comprises at least one subset of lighting devices (31 1,1 , ..., 31 1,m ) coupled to a same output supply pin (101C 1 ) in the plurality of output supply pins (101C 1 , ..., 101C n ). The system further comprises a set of respective electronic switches coupled in series to the lighting devices in the at least one subset of lighting devices (31 1,1 , ..., 31 1,m ). The microcontroller unit (102) is configured to individually control the electronic switches via respective control signals ( P 1,1 , ..., P 1,m ) to individually adjust a brightness of the lighting devices in the at least one subset of lighting devices (31 1,1 , ..., 31 1,m ).
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公开(公告)号：EP4064100A1
公开(公告)日：2022-09-28
申请号：EP22161788.9
申请日：2022-03-14
IPC: G06F21/76
Abstract: A processing system (10a) is described. The processing system (10a) comprises a microprocessor (1020), a hardware circuit (110) configured to change operation as a function of decoded life-cycle data (LC) and a non-volatile memory (104) configured to stored encoded life-cycle data (LCD). A hardware configuration circuit (108) is configured to read the encoded life-cycle data (LCD) from the non-volatile memory (104), decode the encoded life-cycle data (LCD) and provide the decoded life-cycle data (LC) to the hardware circuit (110). The processing system comprises also a reset circuit (116) configured to monitor an external reset signal received via a reset terminal (RP) and, in response to determining that the external reset signal has a first logic level, execute a reset phase (3002), a configuration phase (CP1) and a wait phase (3022), where the reset circuit (116) waits until the external reset signal has a second logic level.
In particular, the processing system comprises also a communication interface (IF_JTAG) activated during the wait phase (3022) and configured to receive a request (REQ), and a hardware verification circuit (130) configured to generate a life-cycle advancement request signal (LCFA_REQ) when the request (REQ) comprises a given reference password (RK) and the reset circuit (116) is in the wait phase (3022). A write circuit (1044w) of the non-volatile memory (104) may thus write one or more bits of the encoded life-cycle data (LCD) stored in the non-volatile memory (104) when the life-cycle advancement request signal (LCFA_REQ) is set, thereby advancing the life-cycle to a given predetermined life-cycle stage.-
Patent Agency Ranking
公开(公告)号：EP3432190B1
公开(公告)日：2020-09-23
申请号：EP18182223.0
申请日：2018-07-06
Applicant: STMicroelectronics Application GmbH
Inventor： COLOMBO, Mr. Roberto
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177.发明授权
公开(公告)号：EP3425552B1
公开(公告)日：2020-09-02
申请号：EP18178541.1
申请日：2018-06-19
Inventor： COLOMBO, Roberto , BERTONI, Guido Marco , ORLANDO, William , VITTIMANI, Roberta
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178.发明授权
公开(公告)号：EP3425551B1
公开(公告)日：2020-07-29
申请号：EP18178475.2
申请日：2018-06-19
Inventor： COLOMBO, Roberto , BERTONI, Guido Marco , ORLANDO, William , VITTIMANI, Roberta
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公开(公告)号：EP3413195B1
公开(公告)日：2020-04-22
申请号：EP18173959.0
申请日：2018-05-24
Applicant: STMicroelectronics Application GmbH
Inventor： COLOMBO, Roberto
IPC: G06F9/445
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180.发明公开
公开(公告)号：EP3425552A1
公开(公告)日：2019-01-09
申请号：EP18178541.1
申请日：2018-06-19
Inventor： COLOMBO, Roberto , BERTONI, Guido Marco , ORLANDO, William , VITTIMANI, Roberta
Abstract: A hardware secure module (HSMa) is described. The hardware secure module (HSMa) comprises a processing unit (106b) and a cryptographic coprocessor (106c). The cryptographic coprocessor (106c) comprises a key storage memory (1064) for storing at least one cryptographic key (MK, CK), a first interface (1068) configured to receive source data (SD) to be processed, a hardware crypto engine (1066) configured to process the source data (SD) as a function of at least one cryptographic key (MK, CK) stored in the key storage memory (1064), a second interface (1060) configured to receive a first cryptographic key (CK) from the processing unit (106b), and a hardware key management circuit (1074) configured to store the first cryptographic key (CK) in the key storage memory (1064).
In particular, the cryptographic coprocessor (106c) comprises a third interface (1070) configured to receive a second cryptographic key (MK), wherein the hardware key management circuit (1074) is configured to store the second cryptographic key (MK) in the key storage memory (1064). The hardware secure element (HSMa) comprises a non-volatile memory (110) adapted to store the second cryptographic key (MK), and a hardware configuration module (106d) configured to read the second cryptographic key (MK) from the non-volatile memory (110) and send the second cryptographic key (MK) to the second interface (1060).
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