公开(公告)号：EP1351065B1

公开(公告)日：2005-06-08

申请号：EP02252426.8

申请日：2002-04-03

Applicant: STMicroelectronics Limited

Inventor： Agarwal, Deepak

IPC: G01R31/3185

CPC classification number: G01R31/318519 ,  G01R31/318516 ,  H03K19/17764

公开(公告)号：EP1536647A1

公开(公告)日：2005-06-01

申请号：EP03257455.0

申请日：2003-11-26

Applicant: STMicroelectronics Limited ,  STMicroelectronics S.r.l.

Inventor： Bolton, Martin ,  Carrano, Michele

IPC: H04N7/26

CPC classification number: H04N7/24 ,  H04N19/42

Abstract: A video decoding circuit comprising: a first video data processor; a second video data processor; and a connection connecting the first video data processor and the second data processor; wherein the first video data processor is arranged to receive a first signal comprising encoded video data, process the first signal to provide a second signal and output said second signal. The first video data processor being arranged to process the first signal dependent on at least part of the received first signal. The second video data processor is arranged to receive at least a part of the second signal, process the at least a part of the second signal to provide a third signal, and output the third signal, the second and third signals comprising a decoded video image stream. The second video data processor is arranged to process the at least part of the second signal dependent on at least part of the at least part of second signal.

Abstract translation: 一种视频解码电路，包括：第一视频数据处理器; 第二视频数据处理器; 以及连接第一视频数据处理器和第二数据处理器的连接; 其中所述第一视频数据处理器被布置为接收包括编码视频数据的第一信号，处理所述第一信号以提供第二信号并输出​​所述第二信号。 所述第一视频数据处理器被布置为依赖于所接收的第一信号的至少一部分来处理所述第一信号。 第二视频数据处理器被布置成接收第二信号的至少一部分，处理第二信号的至少一部分以提供第三信号，并输出第三信号，第二和第三信号包括解码视频图像 流。 第二视频数据处理器被配置为根据第二信号的至少一部分的至少一部分来处理第二信号的至少一部分。

公开(公告)号：EP1531386A1

公开(公告)日：2005-05-18

申请号：EP03257096.2

申请日：2003-11-11

Applicant: STMicroelectronics Limited

Inventor： Raynor, Jeffrey

IPC: G06F3/033

CPC classification number: G06F3/0317 ,  G06F3/03543

Abstract: An optical pointing device is described in which the power consumption is minimised by introducing a variable frame rate controller. Frame rate can be varied through analogue means by way of varying the reference current or through digital means by varying the length of time between successive frames. The variable frame rate controller can accept input from various measurements such as velocity of the device or spatial frequency of the surface on which the device is situated.

Abstract translation: 描述了通过引入可变帧速率控制器来最小化功率消耗的光学指向装置。 可以通过模拟装置通过改变参考电流或通过改变连续帧之间的时间长度的数字方式来改变帧速率。 可变帧速率控制器可以接受来自各种测量的输入，例如设备的速度或设备所在的表面的空间频率。

公开(公告)号：EP1041390B1

公开(公告)日：2005-04-13

申请号：EP00301289.5

申请日：2000-02-18

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert

IPC: G01R31/3185

CPC classification number: G01R31/318552

Abstract: An integrated circuit comprises a serial data input pin and a serial data output pin, on-chip functional circuitry and test logic, a test access port controller connected to effect communication of serial data across the chip boundary via said input and output pins, the test access port controller being connectable to the test logic in a first mode of operation to effect communication of serial test data off-chip, a data adaptor which is connectable to the input and output pins via the test access port controller in a second mode of operation, wherein the data adaptor comprises a first interface for communicating data in the form of serial bits to and from said test access port controller under the control of a first clock signal and a second interface for communicating data in the form of successive sets of parallel data and control signals to and from said on-chip functional circuitry under the control of a second clock signal generated independently of said first clock signal, and wherein said data adaptor comprises data storage means for holding data received in the data adaptor to take into account differences between the first and second clock signals.

公开(公告)号：EP1508853A1

公开(公告)日：2005-02-23

申请号：EP03255133.5

申请日：2003-08-19

Applicant: STMicroelectronics Limited ,  Hewlett-Packard Company

Inventor： Homewood, Fred ,  Faraboschi, Paolo

IPC: G06F9/312 ,  G06F9/315 ,  G06F9/30 ,  G06F12/04

CPC classification number: G06F9/30043 ,  G06F9/30032 ,  G06F9/30145 ,  G06F12/04

Abstract: A method of loading an unaligned word from a specified unaligned word address in a memory, said unaligned word comprising a plurality of indexed portions crossing a word boundary, the method comprising: loading a first aligned word commencing at an aligned word address rounded from said specified unaligned word address; identifying an index representing the location of the unaligned word address relative to the aligned word address; loading a second aligned word commencing at an aligned word address rounded from a second unaligned word address; and combining indexed portions of the first and second aligned words using the identified index to construct the unaligned word.

Abstract translation: 一种从存储器中的指定的未对齐字地址加载未对齐字的方法，所述未对齐字包括与字边界交叉的多个索引部分，所述方法包括：从对应的字地址加载第一对齐字， 未对齐的字地址; 识别表示所述未对齐字地址相对于对齐的字地址的位置的索引; 加载从第二未对齐字地址四舍五入的对齐字地址开始的第二对齐字; 以及使用所识别的索引来组合第一和第二对齐字的索引部分以构造未对齐字。

公开(公告)号：EP1507414A1

公开(公告)日：2005-02-16

申请号：EP03255093.1

申请日：2003-08-15

Applicant: STMicroelectronics Limited

Inventor： Dellow, Andrew ,  Bennett, Peter

IPC: H04N7/16 ,  G06F12/14

CPC classification number: G06F12/1483 ,  H04N21/443 ,  H04N21/4623

Abstract: A privileged data table is provided to maintain a list of those regions of a data memory which contain privileged data. When a data access operation is attempted, a privilege rule enforcer compares the address of the memory being accessed to the list of privileged regions. If the memory address falls within a privileged region then the memory access operation is blocked unless the instruction accessing the memory has been securely authorised by a code verifier. A privileged instruction table is provided to maintain a list of instructions stored in an instruction list that have been verified. When an instruction is fetched from the instruction list, an instruction privilege identifier compares the instruction being fetched with the list of verified instructions, and generates a signal indicating the privilege status of the instruction. Instructions are blocked according to the privilege signal. Only privileged instructions are allowed to modify the contents of the privileged data table and the privileged instruction table. The process of blocking unauthorised memory operations may be performed in accordance with a set of further rules as defined by a rule signal. All components of the system are contained on a single monolithic semiconductor integrated circuit.

Abstract translation: 提供特权数据表以维护包含特权数据的数据存储器的那些区域的列表。 当尝试进行数据访问操作时，特权规则执行者将正在访问的内存的地址与特权区域列表进行比较。 如果存储器地址落在特权区域内，则存储器访问操作被阻止，除非访问存储器的指令已被代码验证者安全地授权。 提供特权指令表以维护存储在已被验证的指令列表中的指令的列表。 当从指令列表中取出指令时，指令特权标识符将所提取的指令与已验证指令的列表进行比较，并产生指示指令的特权状态的信号。 根据特权信号阻止指令。 只允许特权指令修改特权数据表和特权指令表的内容。 可以根据由规则信号定义的一组另外的规则来执行阻止未经授权的存储器操作的过程。 系统的所有组件都包含在单个单片半导体集成电路上。

公开(公告)号：EP0982595B1

公开(公告)日：2005-01-12

申请号：EP99306192.8

申请日：1999-08-04

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert

IPC: G01R31/3185 ,  G06F11/00

CPC classification number: G06F11/267

公开(公告)号：EP1471421A1

公开(公告)日：2004-10-27

申请号：EP03252602.2

申请日：2003-04-24

Applicant: STMicroelectronics Limited

Inventor： Southwell, Trevor

IPC: G06F9/38 ,  G06F12/14

CPC classification number: G06F12/145 ,  G06F9/3842 ,  G06F9/3861 ,  G06F12/1441

Abstract: A method and system for validating speculative load operations. The system identifies speculative load operations that might be executed in a code sequence and after translating the virtual address of the speculative load to a physical address, a speculative load control unit is used to define a plurality of memory regions and has means for checking whether the physical addresses lie within at least one of said defined memory regions. In this way, the control unit allows the mapping of large physical page size to RAM devices and the extra address space is filtered off by the control unit so that speculative loads are not carried out in unknown regions.

Abstract translation: 存储器访问系统定义覆盖存储器空间的几个有效的存储器区域，在存储器空间中存在可用的存储器映射器件之一。 如果接收到的地址位于所定义的存储器区域之一中，系统将验证接收的存储器地址以访问相应的设备，否则返回错误。 还包括用于验证内存地址的方法的独立声明。

公开(公告)号：EP1056192B1

公开(公告)日：2004-10-20

申请号：EP00116212.2

申请日：1996-06-24

Applicant: UNIVERSITY OF BRISTOL ,  STMicroelectronics Limited

Inventor： Beach, Mark Anthony ,  Mattos, Philip Gerad

IPC: H03D3/00

CPC classification number: H03B25/00 ,  H03D3/006

公开(公告)号：EP1079293B1

公开(公告)日：2004-09-15

申请号：EP00303949.2

申请日：2000-05-10

Applicant: STMicroelectronics Limited

Inventor： Barnes, William Bryan, STMicroelectronics, Ltd.

IPC: G05F3/26

CPC classification number: G05F3/262