公开(公告)号：WO1997050221A2

公开(公告)日：1997-12-31

申请号：PCT/US1997010350

申请日：1997-06-17

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  CAHILL, Benjamin, M., III

IPC: H04M00/00

CPC classification number: H04N7/035

Abstract: A hardware system is programmed with a common vertical blanking interval (VBI) scan line decoder to support capture hardware of multiple vendors. The common decoder includes a first and a second function for a capture driver associated with a capture hardware to describe to the common decoder, the sample rate and the line pitch employed by the capture hardware respectively. The common decoder further includes additional functions for the capture driver to confirm the common decoder's presence, register a call back function, specify a channel, and request decoding for a field.

Abstract translation: 硬件系统使用公共垂直消隐间隔（VBI）扫描线解码器编程，以支持多个供应商的捕获硬件。 公共解码器包括用于与捕获硬件相关联的捕获驱动器的第一和第二功能，以分别向公共解码器描述捕获硬件采用的采样率和线间距。 公共解码器还包括用于捕获驱动程序确认共同解码器存在，注册回叫功能，指定信道以及请求字段解码的附加功能。

公开(公告)号：WO1997050128A1

公开(公告)日：1997-12-31

申请号：PCT/US1997009758

申请日：1997-06-09

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  VU, Quat, T. ,  CHIEN, Ling-Chu

IPC: H01L27/10

CPC classification number: H01L23/522 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit device interconnect with controlled inductance. An integrated circuit device includes an insulating layer (25) formed on a substrate (24) and an interconnect (21) disposed on the insulating layer (25) extending along a first path. A dedicated current return path (22) having one end configured to be coupled to ground is disposed on the first insulating layer (25) parallel to the interconnect (21), such that the signal received by the interconnect (21) is returned to ground via the dedicated current return path (22) when the dedicated current return path (22) is coupled to ground. Inductance of the interconnect (21) is thus controlled by reducing the area of the circuit loop (27) formed by the interconnect (21) and the parallel dedicated current return path (22). In one embodiment, the dedicated current return path (32) is formed in an embedded ground plane (34) just above or below the first interconnect (31). In this embodiment, the interconnect (41) and the dedicated current return path (46) together act as a built-in decoupling capacitor, further offsetting the inductive time constant to approach critical damping.

Abstract translation: 集成电路器件与受控电感互连。 集成电路器件包括形成在衬底（24）上的绝缘层（25）和布置在沿着第一路径延伸的绝缘层（25）上的互连（21）。 具有被配置为耦合到地的一端的专用电流返回路径（22）设置在与互连（21）平行的第一绝缘层（25）上，使得由互连（21）接收的信号返回到地 当专用电流返回路径（22）耦合到地时，经由专用电流返回路径（22）。 因此，通过减小由互连（21）和并行专用电流返回路径（22）形成的电路回路（27）的面积来控制互连（21）的电感。 在一个实施例中，专用电流返回路径（32）形成在第一互连（31）正上方或下方的嵌入式接地平面（34）中。 在该实施例中，互连（41）和专用电流返回路径（46）一起用作内置去耦电容器，进一步抵消感应时间常数以接近临界阻尼。

公开(公告)号：WO1997050042A1

公开(公告)日：1997-12-31

申请号：PCT/US1997010447

申请日：1997-06-13

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  MUTHAL, Manish ,  SHAH, Nilesh, V. ,  BAINS, Kuljit

IPC: G06F15/00

CPC classification number: G06F15/167 ,  G06F13/1647

Abstract: A computer system (10), including a graphics controller (18) and a memory controller (14), employs a Shared Frame Buffer Architecture, and accordingly has a shared memory (20) in the form of a bank of DRAMs. The shared memory (320) is accessible by both the memory and graphics controllers. The selector circuit is operable by a logic circuit (231), incorporated within the systems controller (230), which determines whether a memory access request received from the memory controller is to an address in the shared DRAM row (220.2).

Abstract translation: 包括图形控制器（18）和存储器控制器（14）的计算机系统（10）采用共享帧缓冲器体系结构，因此具有一组DRAM形式的共享存储器（20）。 共享存储器（320）可由存储器和图形控制器访问。 选择器电路可由逻辑电路（231）操作，该逻辑电路（231）被并入系统控制器（230）中，逻辑电路确定从存储器控制器接收的存储器访问请求是否是共享DRAM行（220.2）中的地址。

公开(公告)号：WO1997050033A1

公开(公告)日：1997-12-31

申请号：PCT/US1997009759

申请日：1997-06-09

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  CAHILL, Benjamin, M., III

IPC: G06F11/00

CPC classification number: H04N7/0352

Abstract: A hardware system is programmed with a noise tolerant vertical blanking interval (VBI) scan line run-in clock recovery function (10) that determines the phase adjustment for reading sampling data, using only phase error observations that fall within a heavily populated phase error super-subrange, and excluding the remaining phase error observations from the determination, thereby improving the precision of the determination, and reducing unnecessary rejections of VBI scan lines (14).

Abstract translation: 硬件系统被编程具有耐噪声垂直消隐间隔（VBI）扫描线输入时钟恢复功能（10），其确定用于读取采样数据的相位调整，仅使用落入大量相位误差超过的相位误差观测值 - 排除，并从确定中排除剩余的相位误差观察值，从而提高确定的精度，并减少不必要的VBI扫描线（14）的拒绝。

公开(公告)号：WO1997046937A1

公开(公告)日：1997-12-11

申请号：PCT/US1997009571

申请日：1997-05-27

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  REINHARDT, Dennis ,  KARDACH, James, P. ,  HORIGAN, John, W. ,  SONGER, Neil ,  GLEW, Andrew, F.

IPC: G06F09/30

CPC classification number: G06F12/1491 ,  G06F12/0284 ,  G06F12/0802 ,  G06F12/1441 ,  G06F12/1475

Abstract: A novel method and apparatus to cache System Management Mode (SMM) data with other data to improve performance and reduce latency of SMM handler routines. This method and apparatus allows SMM data and non-SMM data to be distinguished in the cache without requiring extra cache bits which can add to the cost of implementation. Since SMM data and non-SMM data can coexist in the cache, there is no need for time consuming cache flush cycles when switching between the two modes (1150). Since SMM data can be cached, performance of SMM routines are improved. This method and apparatus defines the SMRAM address range to be a range of addresses (1110) representable by the tag, but not directly corresponding to installed main memory. When accesses are made to SMRAM addresses, they are redirected to an unused portion of main memory. Protection mechanisms (1150) may be implemented to limit access to these SMRAM addresses when not in SMM.

Abstract translation: 一种用于将系统管理模式（SMM）数据与其他数据进行缓存的新方法和装置，以提高性能并减少SMM处理程序的等待时间。 该方法和装置允许在高速缓存中区分SMM数据和非SMM数据，而不需要增加执行成本的额外的缓存位。 由于SMM数据和非SMM数据可以在高速缓存中共存，因此在两种模式之间切换时不需要耗时的高速缓存刷新周期（1150）。 由于可以缓存SMM数据，因此提高了SMM例程的性能。 该方法和装置将SMRAM地址范围定义为标签可表示的地址范围（1110），但不直接对应于安装的主存储器。 当对SMRAM地址进行访问时，它们被重定向到主存储器的未使用部分。 可以实施保护机制（1150），以在不在SMM中时限制对这些SMRAM地址的访问。

公开(公告)号：WO1997037521A1

公开(公告)日：1997-10-09

申请号：PCT/US1997004685

申请日：1997-03-20

Applicant: INTEL CORPORATION ,  BUTLER, Peter, O. ,  SUAREZ-GARTNER, Ricardo, E.

Inventor： INTEL CORPORATION

IPC: H05K01/11

CPC classification number: H01R12/57 ,  H05K3/303 ,  H05K2201/10568 ,  H05K2201/10598 ,  H05K2201/10734 ,  H05K2203/167 ,  Y02P70/613

Abstract: A method and apparatus for reducing warpage of an assembly substrate (10) and providing registration between a surface mount technology (SMT) component (16) and the assembly substrate. The SMT component (16) includes mounting pins (18) extending from the component and capable of engaging corresponding apertures (14) in the assembly substrate (10). Each mounting pin (18) is registrable with a corresponding aperture (14) in the assembly substrate (10). The mounting pins (18) are capable of providing an interference fit between the SMT component (16) and the assembly substrate (10).

Abstract translation: 一种用于减少组装衬底（10）的翘曲并提供表面贴装技术（SMT）部件（16）和组装衬底之间的对准的方法和装置。 SMT部件（16）包括从部件延伸并能够接合组装衬底（10）中的相应孔（14）的安装销（18）。 每个安装销（18）可与组装衬底（10）中的对应的孔（14）配准。 安装销（18）能够在SMT部件（16）和组装基板（10）之间提供过盈配合。

公开(公告)号：WO1997036466A1

公开(公告)日：1997-10-02

申请号：PCT/US1997003511

申请日：1997-03-07

Applicant: INTEL CORPORATION ,  BARROW, Michael

Inventor： INTEL CORPORATION

IPC: H05K07/06

CPC classification number: H01L23/50 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/3436 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00012

Abstract: A ball grid array (BGA) integrated circuit package (10) which has an outer two-dimensional array of solder balls and a center two-dimensional array of solder balls (34) located on a bottom surface (16) of a package substrate (12). The solder balls are typically reflowed to mount the package to a printed circuit board. Mounted to an opposite surface of the substrate is an integrated circuit (18) that is electrically coupled to the solder balls by internal routing within the package. The outer array of solder balls are located outside of the dimensional profile of the integrated circuit to reduce solder stresses induced by the differential thermal expansion between the integrated circuit and the substrate. The center solder balls are typically routed directly to ground and power pads of the package to provide a direct thermal and electrical path from the integrated circuit to the printed circuit board.

Abstract translation: 一种球栅阵列（BGA）集成电路封装（10），其具有焊盘的外部二维阵列和位于封装基板的底表面（16）上的焊球（34）的中心二维阵列 12）。 焊球通常被回流以将封装安装到印刷电路板上。 安装到基板的相对表面的是集成电路（18），其通过封装内的内部布线电耦合到焊球。 焊球的外部阵列位于集成电路的尺寸轮廓之外，以减少由集成电路和衬底之间的差分热膨胀引起的焊料应力。 中心焊球通常直接路由到封装的地和电源焊盘，以提供从集成电路到印刷电路板的直接热和电路径。

公开(公告)号：WO1997036422A1

公开(公告)日：1997-10-02

申请号：PCT/US1997003763

申请日：1997-03-10

Applicant: INTEL CORPORATION ,  PERRY, Burt ,  BATCHELOR, Steve

Inventor： INTEL CORPORATION

IPC: H04N05/76

CPC classification number: H04N5/765 ,  H04N5/782 ,  H04N7/0887

Abstract: A system (10) that allows a personal computer (14) to remotely control the operation of a video cassette recorder (16). The system includes a radio frequency (RF) transmitter (28) connected to a personal computer (14). The personal computer (14) is programmed to generate a first VCR control signal that is transmitted by the RF transmitter (28) to a RF receiver (30) located within a transceiver base unit (32). The transceiver base unit (32) transmits a second VCR control signal, using an infrared transmitter (34), to the VCR in response to the first VCR control signal. The VCR control signals include commands to record, stop, play, etc. the video cassette recorder. The first VCR control signal can be transmitted in response to a control data signal that is inserted into the vertical blanking interval of a publicly broadcasted video signal that is received and decoded by the computer (14). The control data signal may contain program information which is used to trigger the transmission of the first VCR control signal.

Abstract translation: 一种允许个人计算机（14）远程控制录像机（16）的操作的系统（10）。 该系统包括连接到个人计算机（14）的射频（RF）发射机（28）。 个人计算机（14）被编程为产生由RF发射器（28）发射到位于收发机基座单元（32）内的RF接收器（30）的第一VCR控制信号。 收发机基座单元（32）响应于第一VCR控制信号，将使用红外发射器（34）的第二VCR控制信号发送到VCR。 VCR控制信号包括记录，停止，播放等录像机的命令。 响应于插入到由计算机（14）接收和解码的公开广播的视频信号的垂直消隐间隔的控制数据信号，可以发送第一VCR控制信号。 控制数据信号可以包含用于触发第一VCR控制信号的发送的程序信息。

公开(公告)号：WO1997036287A1

公开(公告)日：1997-10-02

申请号：PCT/US1996013806

申请日：1996-08-28

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  WALKER, Mark, R. ,  KIDDER, Jeffrey ,  KEITH, Michael

IPC: G10L03/00

CPC classification number: G10L19/012

Abstract: An audio stream is analyzed to distinguish silent periods from non-silent periods and an encoded bitstream is generated for the audio stream, wherein the silent periods are represented by one or more sets of canned encoded data corresponding to representative silent periods. In a preferred embodiment, one of the sets of canned encoded data is randomly selected for each silent period. There may be different sets of silent periods corresponding to different types of silent periods, where a particular type of silent period is selected based on some characteristic of the audio stream (e.g., energy level of the silent periods). In addition, the sets of encoded data may be generated from actual silent periods of the audio stream.

Abstract translation: 分析音频流以区分静默期与非静默期，并为音频流生成编码比特流，其中无声期由与代表性静默期对应的一组或多组固定编码数据表示。 在优选实施例中，在每个静默期间随机地选择一组固定编码数据。 可以存在对应于不同类型的无声期间的不同静音期，其中基于音频流的某些特性（例如，无声期间的能量级别）来选择特定类型的无声期间。 此外，可以从音频流的实际静音时段生成编码数据组。

公开(公告)号：WO1997035247A1

公开(公告)日：1997-09-25

申请号：PCT/US1997004028

申请日：1997-03-14

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  HANNAH, Eric, C.

IPC: G06F03/04

CPC classification number: H04N1/00238 ,  H04N1/00236 ,  H04N1/00241

Abstract: A copier (10) for rendering an image of an object onto a physical medium includes a scanner (60), a printer (80) and an external processor (30). The scanner (60) and the printer (80) are coupled to the external processor (30) by a high-speed serial bus (61) having a latency and a maximum signal transmission rate sufficient to enable transmission to the external processor (30) of the digital image signal generated by the scanner (60) which represent the image of the object without prior interim storage of the digital image signals in a buffer on board the scanner (60). The high-speed serial bus (61) further has a latency and a maximum signal transmission rate sufficient to enable transmission of the digital image signals from the external processor (30) to the printer (80) for rendering the digital image signals in a buffer on board the printer (80). In an embodiment, the external processor (30) is capable of processing the digital image signals and the scanner (60) is capable of transmitting the digital image signals without prior on-board digital processing of the digital image signals in the scanner (60) and the printer (80) is capable of rendering the digital image signals without prior on-board digital processing of the digital image signals in the printer (80).

Abstract translation: 用于将物体的图像呈现到物理介质上的复印机（10）包括扫描器（60），打印机（80）和外部处理器（30）。 扫描器（60）和打印机（80）通过高速串行总线（61）耦合到外部处理器（30），该高速串行总线具有足以使能够传送到外部处理器（30）的等待时间和最大信号传输速率， 由扫描器（60）生成的数字图像信号（其代表对象的图像）而没有将数字图像信号预先临时存储在扫描器（60）上的缓冲器中。 高速串行总线（61）还具有足以使数字图像信号从外部处理器（30）传输到打印机（80）的延迟和最大信号传输速率，以将数字图像信号呈现在缓冲器 在打印机（80）上。 在一个实施例中，外部处理器（30）能够处理数字图像信号，并且扫描器（60）能够传输数字图像信号而无需先前对扫描器（60）中的数字图像信号进行数字处理， 并且打印机（80）能够呈现数字图像信号，而无需对打印机（80）中的数字图像信号进行预先的板载数字处理。