中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

55 records (took 0.029 seconds)

    EXCHANGING ECC METADATA BETWEEN MEMORY AND HOST SYSTEM
    1.
    发明申请
    EXCHANGING ECC METADATA BETWEEN MEMORY AND HOST SYSTEM 审中-公开
    存储器和主机系统之间交换ECC元数据

    公开(公告)号：WO2016048634A1

    公开(公告)日：2016-03-31

    申请号：PCT/US2015/048776

    申请日：2015-09-08

    Applicant: INTEL CORPORATION

    Inventor： BONEN, Nadav ,  BAINS, Kuljit ,  HALBERT, John

    IPC: G06F11/10 ,  G06F12/00 ,  G06F13/16

    CPC classification number: G06F11/1076 ,  G06F11/1004 ,  G06F11/1048

    Abstract: Exposing internal error correction bits from a memory device for use as metadata bits by an external memory controller. In a first mode the memory device applies internal error correction bits for internal error correction at the memory device. In a second mode the memory device exposes the internal error correction bits to the memory controller to allow the memory controller to use the data.

    Abstract translation: 从存储器件中公开内部纠错位，用于由外部存储器控制器用作元数据位。 在第一模式中，存储器件在存储器件处应用用于内部纠错的内部纠错位。 在第二模式中，存储器件将内部纠错位公开到存储器控制器以允许存储器控制器使用数据。

    TECHNOLOGY TO PROVIDE ACCURATE TRAINING AND PER-BIT DESKEW CAPABILITY FOR HIGH BANDWIDTH MEMORY INPUT/OUTPUT LINKS
    3.
    发明申请
    TECHNOLOGY TO PROVIDE ACCURATE TRAINING AND PER-BIT DESKEW CAPABILITY FOR HIGH BANDWIDTH MEMORY INPUT/OUTPUT LINKS 审中-公开

    公开(公告)号：WO2022051046A1

    公开(公告)日：2022-03-10

    申请号：PCT/US2021/043915

    申请日：2021-07-30

    Applicant: INTEL CORPORATION

    Inventor： LANKA, Narasimha ,  BAINS, Kuljit ,  YERVA, Lohit

    IPC: G06F3/06 ,  G06N20/00 ,  G06F13/16 ,  G06F11/10

    Abstract: Systems, apparatuses and methods may provide for technology that programs a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word (DWORD) and at least two of the plurality of seed values differ from one another. The technology may also train a link coupled to the plurality of LFSRs, wherein the plurality of seed values cause a parity bit associated with the DWORD to toggle while the link is being trained. In one example, the technology also automatically selects the plurality of seed values based on one or more of an expected traffic pattern on the link (e.g., after training) or a deskew constraint associated with the link.

    DOUBLE DATA RATE COMMAND BUS
    4.
    发明申请
    DOUBLE DATA RATE COMMAND BUS 审中-公开
    双数据速率命令总线

    公开(公告)号：WO2018038883A1

    公开(公告)日：2018-03-01

    申请号：PCT/US2017/045046

    申请日：2017-08-02

    Applicant: INTEL CORPORATION

    Inventor： VERGIS, George ,  BAINS, Kuljit

    IPC: G06F13/42

    Abstract: A memory subsystem includes a command address bus capable to be operated at double data rate. A memory circuit includes N command signal lines that operate at a data rate of 2R to receive command information from a memory controller. The memory circuit includes 2N command signal lines that operate at a data rate of R to transfer the commands to one or more memory devices. While ratios of 1:2 are specified, similar techniques can be used to send command signals at higher data rates over fewer signal lines from a host to a logic circuit, which then transfers the command signals at lower data rates over more signal lines.

    Abstract translation: 存储器子系统包括能够以双倍数据速率操作的命令地址总线。 存储器电路包括以2R的数据速率操作以从存储器控制器接收命令信息的N个命令信号线。 存储器电路包括以数据速率R操作的2N个命令信号线以将命令传送到一个或多个存储器装置。 虽然规定了1：2的比率，但类似的技术可用于以较高的数据速率通过较少的信号线从主机向逻辑电路发送命令信号，然后以较低的数据速率通过更多的信号线传送命令信号。 / p>

    SELECTIVE CONTROL OF ON-DIE TERMINATION IN A MULTI-RANK SYSTEM
    5.
    发明申请
    SELECTIVE CONTROL OF ON-DIE TERMINATION IN A MULTI-RANK SYSTEM 审中-公开
    多级系统中的终端终止的选择性控制

    公开(公告)号：WO2016014212A1

    公开(公告)日：2016-01-28

    申请号：PCT/US2015/038003

    申请日：2015-06-26

    Applicant: INTEL CORPORATION

    Inventor： BAINS, Kuljit ,  BONEN, Nadav

    IPC: G11C7/00 ,  G11C7/10

    CPC classification number: H03K19/0005 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/4086 ,  H03K19/0008 ,  H03K19/017545 ,  H03K19/01825 ,  H03K19/018557

    Abstract: A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.

    Abstract translation: 存储器子系统包括多器件封装，其包括被组织为多级存储器的多个存储器件。 用于存储器子系统的控制单元向存储器的一些或全部行同时发送存储器访问命令，并且触发接收存储器访问命令的所有存储器等级的一部分以改变管芯终端（ODT）设置。 选择其中一个行执行存储器访问命令，并且在所有等级触发以改变ODT设置的情况下执行命令具有改变的ODT设置。

    MEMORY BROADCAST COMMAND
    6.
    发明申请
    MEMORY BROADCAST COMMAND 审中-公开
    内存广播命令

    公开(公告)号：WO2015041979A1

    公开(公告)日：2015-03-26

    申请号：PCT/US2014/055629

    申请日：2014-09-15

    Applicant: INTEL CORPORATION

    Inventor： BAINS, Kuljit ,  VOGT, Pete

    IPC: G06F13/00 ,  G06F9/30 ,  G06F12/00

    CPC classification number: G11C7/1072 ,  G06F13/1668

    Abstract: Apparatus, systems, and methods to broadcast a memory command are described. In one embodiment, a memory controller comprising logic to insert a first predetermined value into an all ranks parameter in a memory command, and transmit the memory command to a memory device. Other embodiments are also disclosed and claimed.

    Abstract translation: 描述用于广播存储器命令的装置，系统和方法。 在一个实施例中，一种存储器控制器，包括将第一预定值插入到存储器命令中的全部等级参数中的逻辑，并将存储器命令发送到存储器件。 还公开并要求保护其他实施例。

    STAGGERING INITIATION OF REFRESH IN A GROUP OF MEMORY DEVICES
    9.
    发明申请
    STAGGERING INITIATION OF REFRESH IN A GROUP OF MEMORY DEVICES 审中-公开
    在一组存储设备中刷新刷新指令

    公开(公告)号：WO2018063697A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2017/049315

    申请日：2017-08-30

    Applicant: INTEL CORPORATION

    Inventor： TOMISHIMA, Shigeki ,  HALBERT, John ,  BAINS, Kuljit

    IPC: G11C11/406 ,  G11C11/4076

    Abstract: Memory refresh includes timing offsets for different memory devices, to initiate refresh of different memory devices at different times. A memory controller sends a refresh command to cause refresh of multiple memory devices. In response to the refresh command, the multiple memory devices initiate refresh with timing offsets relative to another of the memory devices. The timing offsets reduce the instantaneous power surge associated with all memory devices starting refresh simultaneously.

    Abstract translation: 存储器刷新包括不同存储器设备的定时偏移，以在不同时间启动不同存储器设备的刷新。 内存控制器发送刷新命令以引起多个内存设备的刷新。 响应于刷新命令，多个存储器设备利用相对于另一个存储器设备的定时偏移来发起刷新。 时序偏移减少了与所有存储器设备同时开始刷新相关的瞬时功率浪涌。

    INTERNAL ERROR CHECKING AND CORRECTION (ECC) WITH EXTRA SYSTEM BITS
    10.
    发明申请
    INTERNAL ERROR CHECKING AND CORRECTION (ECC) WITH EXTRA SYSTEM BITS 审中-公开
    内部错误检查和纠正（ECC）与额外的系统位

    公开(公告)号：WO2017192626A1

    公开(公告)日：2017-11-09

    申请号：PCT/US2017/030695

    申请日：2017-05-02

    Applicant: INTEL CORPORATION

    Inventor： BAINS, Kuljit ,  NALE, Bill ,  AGARWAL, Rajat

    IPC: G11C29/42 ,  G06F11/10 ,  G11C11/409

    Abstract: A memory subsystem includes a data bus to couple a memory controller to one or more memory devices. The memory controller and one or more memory devices transfer data for memory access operations. The data transfer includes the transfer of data bits and associated check bits over a transfer cycle burst. The memory devices include internal error checking and correction (ECC) separate from the system ECC managed by the memory controller. With a 2N transfer cycle for 2^N data bits for a memory device, the memory devices can provide up to 2N memory locations for N+1 internal check bits, which can leave up to (2N minus (N+1)) extra bits to be used by the system for more robust ECC.

    Abstract translation: 存储器子系统包括数据总线以将存储器控制器耦合到一个或多个存储器设备。 存储器控制器和一个或多个存储器设备传输用于存储器访问操作的数据。 数据传输包括通过传输周期突发传输数据位和相关的校验位。 存储器设备包括与由存储器控制器管理的系统ECC分开的内部错误检查和校正（ECC）。 对于存储器件，2 ^ N个数据位的2N传输周期对于N + 1个内部校验位可以提供高达2N个存储器位置，这可以留下多达（2N减（N + 1））个额外位 供系统使用，以获得更强大的ECC。

Patent Agency Ranking