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公开(公告)号：US09572903B2
公开(公告)日：2017-02-21
申请号：US14883804
申请日：2015-10-15
Applicant: Sensor Electronic Technology, Inc.
Inventor： Alexander Dobrinsky , Michael Shur , Remigijus Gaska , Timothy James Bettles
CPC classification number: A61L2/10 , A41D13/002 , A61L2/24 , A61L9/00 , A61L9/20 , A61L2202/14 , A61L2209/111 , A61L2209/14 , G01J1/429 , G01N21/6456 , G01N21/6486 , G01N2201/0221 , G09B5/06 , G09B19/24
Abstract: A system capable of detecting and/or sterilizing surface(s) of an object using ultraviolet radiation is provided. The system can include a disinfection chamber and/or handheld ultraviolet unit, which includes ultraviolet sources for inducing fluorescence in a contaminant and/or sterilizing a surface of an object. The object can comprise a protective suit, which is worn by a user and also can include ultraviolet sources for disinfecting air prior to the air entering the protective suit. The system can be implemented as a multi-tiered system for protecting the user and others from exposure to the contaminant and sterilizing the protective suit after exposure to an environment including the contaminant.
Abstract translation: 提供一种能够使用紫外线辐射来检测和/或消毒物体表面的系统。 该系统可以包括消毒室和/或手持式紫外线单元，其包括用于在污染物中诱导荧光和/或消毒物体表面的紫外线源。 该物体可以包括用户佩戴的防护服，并且还可以包括用于在空气进入防护服之前对空气进行消毒的紫外线源。 该系统可以实现为多层系统，用于在暴露于包括污染物的环境之后，保护使用者和其他人免受暴露于污染物和对防护服进行消毒。
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公开(公告)号：US20170005246A1
公开(公告)日：2017-01-05
申请号：US15198569
申请日：2016-06-30
Applicant: Sensor Electronic Technology, Inc.
Inventor： Michael Shur , Alexander Dobrinsky
CPC classification number: H01L33/42 , H01L24/00 , H01L31/00 , H01L33/10 , H01L33/32 , H01L33/40 , H01L2933/0016 , H01S5/0224 , H01S5/0421 , H01S5/34333
Abstract: A multi-layered contact to a semiconductor structure and a method of making is described. In one embodiment, the contact includes a discontinuous Chromium layer formed over the semiconductor structure. A discontinuous Titanium layer is formed directly on the Chromium layer, wherein portions of the Titanium layer extend into at least some of the discontinuous sections of the Chromium layer. A discontinuous Aluminum layer is formed directly on the Chromium layer, wherein portions of the Aluminum layer extend into at least some of the discontinuous sections of the Titanium layer and the Chromium layer.
Abstract translation: 描述了与半导体结构的多层接触和制造方法。 在一个实施例中，触点包括形成在半导体结构上的不连续的铬层。 直接在铬层上形成不连续的钛层，其中钛层的部分延伸到铬层的至少一些不连续部分。 直接在铬层上形成不连续的铝层，其中铝层的部分延伸到钛层和铬层的至少一些不连续部分。
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公开(公告)号：US09537054B2
公开(公告)日：2017-01-03
申请号：US14686845
申请日：2015-04-15
Applicant: Sensor Electronic Technology, Inc.
Inventor： Daniel D. Billingsley , Robert M. Kennedy , Wenhong Sun , Rakesh Jain , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
CPC classification number: H01L33/12 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L29/155 , H01L29/2003 , H01L33/0025 , H01L33/007 , H01L33/0075 , H01L33/06 , H01L33/20 , H01L33/24 , H01L33/32 , H01L2224/16225
Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
Abstract translation: 提供了用于制造光电子器件的异质结构。 异质结构包括诸如n型接触或包覆层的层，其包括插入其中的薄子层。 薄的子层可以遍及整个层间隔开，并由用于该层的材料制成的中间子层隔开。 薄的子层可以具有与插入的子层不同的组成，其在异质结构的生长期间改变应力存在。
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公开(公告)号：US20160355947A1
公开(公告)日：2016-12-08
申请号：US15173660
申请日：2016-06-05
Applicant: Sensor Electronic Technology, Inc.
Inventor： Alexander Dobrinsky , Michael Shur
IPC: C30B25/16 , C30B25/12 , C23C16/458 , C23C16/46 , C23C16/455 , C23C16/52 , C30B25/10 , C30B25/14
CPC classification number: C30B25/16 , C23C16/4586 , C23C16/46 , C23C16/52 , C30B25/10
Abstract: An approach for heating a susceptor during an epitaxial growth process of semiconductor layers in an epitaxial growth chamber is described. A main heating unit heats a region of the susceptor supporting a wafer. An auxiliary heating unit supports the main heating unit in heating the susceptor when the temperature distribution over the surface of the wafer fails to satisfy a target temperature distribution. The control unit monitors the temperature distribution over the surface of the wafer while the susceptor is heated by both the main heating unit and the auxiliary heating unit and adjusts at least one of a multitude of operating parameters for the auxiliary heating unit in response to determining that the temperature distribution over the surface of the wafer while the susceptor is heated by the main heating unit and the auxiliary heating unit is failing to satisfy the target temperature distribution.
Abstract translation: 描述了在外延生长室中的半导体层的外延生长过程期间加热基座的方法。 主加热单元加热支撑晶片的基座的区域。 当晶片表面上的温度分布不能满足目标温度分布时，辅助加热单元支撑主加热单元加热基座。 所述控制单元监测所述晶片表面上的温度分布，同时所述基座被所述主加热单元和所述辅助加热单元加热，并响应于确定所述辅助加热单元的多个操作参数中的至少一个而调整 当基座被主加热单元和辅助加热单元加热时，晶片表面上的温度分布不能满足目标温度分布。
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公开(公告)号：US20160343902A1
公开(公告)日：2016-11-24
申请号：US15231062
申请日：2016-08-08
Applicant: Sensor Electronic Technology, Inc.
Inventor： Michael Shur , Alexander Dobrinsky
CPC classification number: H01L33/06 , H01L33/0045 , H01L33/14 , H01L33/18 , H01L33/32 , H01L33/38 , H01L33/40
Abstract: A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another. Furthermore, the superlattice layer can be configured to be at least partially transparent to radiation, such as ultraviolet radiation.
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Patent Agency Ranking
公开(公告)号：US20160343901A1
公开(公告)日：2016-11-24
申请号：US15225382
申请日：2016-08-01
Applicant: Sensor Electronic Technology, Inc.
Inventor： Michael Shur , Rakesh Jain , Maxim S. Shatalov , Alexander Dobrinsky , Jinwei Yang , Remigijus Gaska , Mikhail Gaevski
CPC classification number: H01L33/06 , H01L33/007 , H01L33/18 , H01L33/30 , H01L33/382 , H01L2224/14 , H01S5/0224 , H01S5/3209 , H01S5/3413 , H01S5/34333
Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.
Abstract translation: 提供了包括包括多个组成不均匀区域的半导体层的器件。 多个组成不均匀区域的平均带隙与半导体层的剩余部分的平均带隙之间的差可以是至少热能。 此外，多个组成不均匀区域的特征尺寸可以小于半导体层的位错密度的倒数。
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公开(公告)号：US09502509B2
公开(公告)日：2016-11-22
申请号：US15083423
申请日：2016-03-29
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Jinwei Yang , Wenhong Sun , Rakesh Jain , Michael Shur , Remigijus Gaska
IPC: H01L31/00 , H01L29/15 , H01L29/205 , H01L29/20 , H01L29/06
CPC classification number: H01L29/158 , H01L21/0237 , H01L21/02458 , H01L21/02505 , H01L21/02507 , H01L21/02513 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/0265 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L33/007 , H01L33/12
Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
Abstract translation: 提供了诸如III族氮化物基半导体结构的半导体结构。 半导体结构包括含有半导体层的空腔。 含腔的半导体层可以具有大于两个单层和多个空腔的厚度。 空腔可以具有至少一纳米的特征尺寸和至少五纳米的特征分离。
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公开(公告)号：US20160322466A1
公开(公告)日：2016-11-03
申请号：US15208309
申请日：2016-07-12
Applicant: Sensor Electronic Technology, Inc.
Inventor： Grigory Simin , Mikhail Gaevski , Michael Shur , Remigijus Gaska
IPC: H01L29/20 , H01L29/16 , H01L29/423 , H01L29/66 , H01L29/778 , H01L29/861 , H01L29/78
CPC classification number: H01L29/2003 , H01L23/367 , H01L29/0623 , H01L29/0657 , H01L29/1087 , H01L29/402 , H01L29/404 , H01L29/405 , H01L29/41758 , H01L29/41766 , H01L29/4232 , H01L29/4236 , H01L29/4238 , H01L29/6609 , H01L29/66446 , H01L29/66477 , H01L29/7786 , H01L29/78 , H01L29/7831 , H01L29/7838 , H01L29/861 , H01L29/8613 , H01L29/872 , H01L29/93 , H01L2924/0002 , H01L2924/00
Abstract: A lateral semiconductor device and/or design including a space-charge generating layer and an electrode or a set of electrodes located on an opposite side of a device channel as contacts to the device channel is provided. The space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the contacts to the device channel.
Abstract translation: 提供了一种横向半导体器件和/或设计，其包括空间电荷产生层和位于器件沟道的相对侧上的电极或电极组，作为与器件通道的接触。 空间电荷产生层被配置为响应于施加到器件通道的触点的工作电压而形成空间电荷区域以至少部分地耗尽器件沟道。
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公开(公告)号：US20160260867A1
公开(公告)日：2016-09-08
申请号：US15069272
申请日：2016-03-14
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Remigijus Gaska , Jinwei Yang , Michael Shur , Alexander Dobrinsky
CPC classification number: H01L33/06 , B82Y10/00 , B82Y20/00 , H01L29/15 , H01L29/155 , H01L29/2003 , H01L29/201 , H01L29/207 , H01L33/0075 , H01L33/04 , H01L33/145 , H01L33/32 , H01L33/325 , H01S5/2009 , H01S5/3211 , H01S5/3216 , H01S5/3407 , H01S5/34333
Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).
Abstract translation: 提供了一种用于设计和/或制造包括量子阱和相邻屏障的结构的解决方案。 选择量子阱和相邻屏障之间的目标频带不连续性以与量子阱和/或屏障的掺杂剂的活化能一致。 例如，可以选择目标价带不连续性，使得相邻势垒中的掺杂剂的掺杂剂能级与量子阱的价态能带边缘和/或价态能带中的自由载流子的基态能量一致 量子阱。 另外，可以选择量子阱和/或相邻势垒的目标掺杂水平以促进穿过势垒的空穴的实际空间传递。 可以形成量子阱和相邻势垒，使得实际的带不连续性和/或实际掺杂水平对应于相关目标。
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公开(公告)号：US09412902B2
公开(公告)日：2016-08-09
申请号：US14628281
申请日：2015-02-22
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Jinwei Yang , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
CPC classification number: H01L33/12 , G06F17/505 , H01L33/0025 , H01L33/007 , H01L33/0075 , H01L33/06 , H01L33/145 , H01L33/24 , H01L33/32 , H01L33/38 , H01L33/46
Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.
Abstract translation: 提供一种半导体结构，包括缓冲结构和与缓冲结构的第一侧相邻形成的一组半导体层。 缓冲结构可以具有有效的晶格常数和厚度，使得该组半导体层在室温下的总应力是压缩的，并且在约0.1GPa和2.0GPa之间的范围内。 可以使用选择的一组生长参数来生长缓冲结构，以实现目标有效晶格常数a，缓冲结构生长期间存在的控制应力和/或半导体结构冷却后存在的控制应力。
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