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    Alignment of single and multi-mode optical fibers using piezoelectric actuators
    181.
    发明授权
    Alignment of single and multi-mode optical fibers using piezoelectric actuators 有权

    公开(公告)号：US10649158B2

    公开(公告)日：2020-05-12

    申请号：US16098406

    申请日：2016-07-01

    Applicant: Intel Corporation

    Inventor： Johanna M. Swan ,  Aleksandar Aleksov ,  Sasha N. Oster ,  Feras Eid ,  Baris Bicen ,  Thomas L. Sounart ,  Shawna M. Liff ,  Valluri R. Rao

    IPC: G02B6/42 ,  G02B6/36

    Abstract: Embodiments of the invention include an optoelectronic package that allows for in situ alignment of optical fibers. In an embodiment, the optoelectronic package may include an organic substrate. Embodiments include a cavity formed into the organic substrate. Additionally, the optoelectronic package may include an actuator formed on the organic substrate that extends over the cavity. In one embodiment, the actuator may include a first electrode, a piezoelectric layer formed on the first electrode, and a second electrode formed on the piezoelectric layer. According to an additional embodiment of the invention, the actuator may include a first portion and a second portion. In order to allow for resistive heating and actuation driven by thermal expansion, a cross-sectional area of the first portion of the beam may be greater than a cross-sectional area of the second portion of the beam.

    Stretchable computing device
    182.
    发明授权
    Stretchable computing device 有权

    公开(公告)号：US10327331B2

    公开(公告)日：2019-06-18

    申请号：US15762811

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： Nadine L. Dabby ,  Adel A. Elsherbini ,  Braxton Lathrop ,  Sasha N. Oster ,  Aleksandar Aleksov

    IPC: H05K1/02 ,  G06F1/16 ,  H05K1/11

    Abstract: Some forms relate to a stretchable computing device. The stretchable computing device includes a first layer that includes electrical interconnects at a first density wherein the first layer includes a first electronic component; a stretchable second layer electrically connected to the first layer, wherein the stretchable second layer includes electrical interconnects at a second density that is less than the first density, wherein the second layer includes a second electronic component; and a stretchable third layer electrically connected to the stretchable second layer, wherein the stretchable third layer includes electrical interconnects at a third density that is less than the second density.

    Package assembly with hermetic cavity
    184.
    发明授权
    Package assembly with hermetic cavity 有权

    公开(公告)号：US10314171B1

    公开(公告)日：2019-06-04

    申请号：US15859321

    申请日：2017-12-29

    Applicant: Intel Corporation

    Inventor： Aleksandar Aleksov ,  Feras Eid ,  Johanna M. Swan

    IPC: H05K1/18 ,  H05K3/46 ,  H05K1/03 ,  H05K1/09 ,  H05K3/18 ,  H05K3/34

    Abstract: Apparatuses, systems and methods associated with hermetic encapsulation for package assemblies are disclosed herein. In embodiments, a package assembly may include a package substrate that includes a guard ring, wherein the guard ring extends from a surface of the package substrate and around a circumference of a cavity. The package assembly may further include a component coupled to the guard ring by a solder joint along an entirety of the guard ring, wherein the cavity is located between the package substrate and the component and the cavity is hermetically-sealed via the guard ring and the solder joint. Other embodiments may be described and/or claimed.

    Complementary tunneling FET devices and method for forming the same
    185.
    发明授权
    Complementary tunneling FET devices and method for forming the same 有权

    公开(公告)号：US10269942B2

    公开(公告)日：2019-04-23

    申请号：US15673359

    申请日：2017-08-09

    Applicant: Intel Corporation

    Inventor： Aleksandar Aleksov

    IPC: H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L29/267 ,  H01L29/423 ,  H01L51/05 ,  H01L29/24 ,  H01L29/786 ,  H01L51/00 ,  H01L21/8258 ,  H01L29/78

    Abstract: Described is an apparatus forming complementary tunneling field effect transistors (TFETs) using oxide and/or organic semiconductor material. One type of TFET comprises: a substrate; a doped first region, formed above the substrate, having p-type material selected from a group consisting of Group III-V, IV-IV, and IV of a periodic table; a doped second region, formed above the substrate, having transparent oxide n-type semiconductor material; and a gate stack coupled to the doped first and second regions. Another type of TFET comprises: a substrate; a doped first region, formed above the substrate, having p-type organic semiconductor material; a doped second region, formed above the substrate, having n-type oxide semiconductor material; and a gate stack coupled to the doped source and drain regions. In another example, TFET is made using organic only semiconductor materials for active regions.

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