Abstract:
A viterby-detector recovers servo data from a servo signal generated by a read-write head, and determines the head-connection polarity from the recovered servo data. Such a detector allows a servo circuit to compensate for a reversed-connected read-write head, and thus allows a manufacturer to forego time-consuming and costly testing to determine whether the head is correctly connected to the servo circuit.
Abstract:
An encoder for encoding data, the encoder operable to generate a code word comprising: a first group of data bits; code bits that represent a second group of data bits; and a minimum probability of transitions among the code bits.
Abstract:
An integrated circuit temperature sensor includes a sensing circuit operable to determine whether the integrated circuit is currently exposed to one of a relatively low temperature or a relatively high temperature. A selection circuit operates to select a measured voltage across the base-emitter of a bipolar transistor of the integrated circuit if the sensing circuit indicates that the integrated circuit is currently exposed to the relatively low temperature or, alternatively, select a measured delta voltage across the base-emitter of the bipolar transistor of the integrated circuit if the sensing circuit indicates that the integrated circuit is currently exposed to the relatively high temperature. A comparator then compares the selected measured voltage across the base-emitter of the bipolar transistor against a first reference voltage indicative of a too cold temperature condition or compares the selected measured delta voltage across the base-emitter of the bipolar transistor against a second reference voltage indicative of a too hot temperature condition. As a result of the comparison, detection may be made as to whether the integrated circuit is currently exposed to one of either a too cold or too hot temperature. In a test mode, the circuit is exposed to a readily available temperature, such as room temperature, and the measured delta voltage across the base-emitter and/or the measured voltage across the base-emitter are scaled in accordance with that available temperature for application to the comparator. Alternatively, in test mode the reference voltages are scaled to intersect with the measured delta voltage across the base-emitter and/or the measured voltage across the base-emitter at the available temperature.
Abstract:
A single sideband mixer circuit includes a voltage controlled oscillator operable to provide a tunable frequency f1. The mixer circuit outputs a frequency signal at a frequency f1 ± f2. A tracking filter operates to filter the frequency signal and generate a first output signal at the frequency f1 ± f2. A resonance frequency fr of the tracking filter is tunable to substantially match the frequency f1 ± f2 of the frequency signal. The output signal of the tracking filter may be processed by a phase lock loop circuit to generate a control signal for controlling the setting of the tunable frequency f1 and resonance frequency fr. Alternatively, the output signal of the tracking filter may be divided and the divided signal processed by a phase lock loop circuit to generate the control signal for controlling setting of the tunable frequency f1 and resonance frequency fr.
Abstract:
A programmable priority encoder is disclosed for use with the device such as a Content Addressable Memory (CAM) device having a plurality of array objects to be encoded in binary and arranged in row and columns. Match lines are adapted to be connected to a plurality of arrayed objects associated with respective rows. A plurality of encoder cells, each having a memory element and forming an encoder block are arranged in rows. Precharged bus lines are operative with the encoder cells and match lines. The precharged bus lines are discharged indicating a match and priority is assigned to rows based on logic values stored within the memory elements of the encoder cell.
Abstract:
A ROM patching apparatus for use in a data processing system that executes instruction code stored the ROM. The ROM patching apparatus comprises: 1) a patch buffer for storing a first replacement cache line containing a first new instruction suitable for replacing at least a portion of the code in the ROM; 2) a lockable cache; 3) core processor logic operable to read from an associated memory a patch table containing a first table entry, the first table entry containing 1) the first new instruction and 2) a first patch address identifying a first patched ROM address of the at least a portion of the code in the ROM. The core processor logic loads the first new instruction from the patch table into the patch buffer, stores the first replacement cache line from the patch buffer into the lockable cache, and locks the first replacement cache line into the lockable cache.