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    Temperature tamper detection circuit and method
    2.
    发明公开
    Temperature tamper detection circuit and method 有权
    用于可编程篡改检测电路测试电路

    公开(公告)号：EP1788581A3

    公开(公告)日：2007-08-22

    申请号：EP06255947.1

    申请日：2006-11-21

    Applicant: STMicroelectronics, Inc.

    Inventor： McClure, David C. ,  Saw, Sooping

    IPC: G11C16/20 ,  G11C16/22 ,  G11C17/16 ,  G06K19/073 ,  G06F21/00

    CPC classification number: G01K3/005 ,  G01K7/015

    Abstract: An integrated circuit temperature sensor includes a sensing circuit operable to determine whether the integrated circuit is currently exposed to one of a relatively low temperature or a relatively high temperature. A selection circuit operates to select a measured voltage across the base-emitter of a bipolar transistor of the integrated circuit if the sensing circuit indicates that the integrated circuit is currently exposed to the relatively low temperature or, alternatively, select a measured delta voltage across the base-emitter of the bipolar transistor of the integrated circuit if the sensing circuit indicates that the integrated circuit is currently exposed to the relatively high temperature. A comparator then compares the selected measured voltage across the base-emitter of the bipolar transistor against a first reference voltage indicative of a too cold temperature condition or compares the selected measured delta voltage across the base-emitter of the bipolar transistor against a second reference voltage indicative of a too hot temperature condition. As a result of the comparison, detection may be made as to whether the integrated circuit is currently exposed to one of either a too cold or too hot temperature.

    Circuit and method for asynchronously accessing a ferroelectric memory device
    5.
    发明公开
    Circuit and method for asynchronously accessing a ferroelectric memory device 有权
    异步存取方法和电路，用于存储器阵列ferroelekrische

    公开(公告)号：EP1225594A3

    公开(公告)日：2003-12-03

    申请号：EP01310118.3

    申请日：2001-12-03

    Applicant: STMicroelectronics, Inc.

    Inventor： McClure, David C.

    IPC: G11C11/22 ,  G11C29/00

    CPC classification number: G11C11/22

    Abstract: A circuit and method for performing a stress test on a ferroelectric memory device. The memory device includes a memory cell array having a plurality of row lines, column lines and plate lines. The memory device further includes test circuitry for receiving at least one test control signal and in response to the at least one test control signal allowing a voltage differential to be applied between the column lines and the plate lines, so that a stress voltage may be applied across each of the memory cells at one time.

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