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公开(公告)号：GB2336059A
公开(公告)日：1999-10-06
申请号：GB9807292
申请日：1998-04-03
Applicant: KOREA TELECOMMUNICATION
Inventor： KIM HAN HO , AHN TAE HYO , CHUN JOONG CHANG , PARK JIN SOO , YOON YONG HO , HWANG WON TAIK
Abstract: A raster type map display method displays various scales of stored raster type maps according to the display scale on screen. The scale of raster type map to be used is determined according to the display scale of the screen. If the region to be displayed does not have any corresponding scale of raster type map, the largest scale of raster type map among the lower and available scales of raster type maps is used for displaying. Also, different reference values for selecting a raster type map are used according to an expansion mode or reduction mode. Accordingly, a high display resolution can be effectively attained and the management of memory can be efficiently performed. In addition, processing speed is increased and the frequent replacement of the map is prevented.
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公开(公告)号：FR2754083B1
公开(公告)日：1999-06-18
申请号：FR9712220
申请日：1997-10-01
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN IL SONG
Abstract: A multiplier capable of removing nonlinear current using current mirror circuits. The multiplier uses MOSFET and BJT devices by the BiCOMS processes. The multiplier includes three current mirror circuits. A first current mirror includes a BJT Q3 and a BJT Q5 and also the BJT Q3 is coupled in series to the n-channel MOSFET M1 between the voltage V1 and a ground voltage level. A second current mirror includes a BJT Q7 and a BJT Q8. A third current mirror includes a BJT Q4 and a BJT Q6. Consequently, input voltage signals V1 and Vdc applied to the n-channel MOSFETs M1 determine the current I1 and input voltage signals V1 and V2 applied to the n-channel MOSFET M2 determine the current I2.
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公开(公告)号：SE509050C2
公开(公告)日：1998-11-30
申请号：SE9000859
申请日：1990-03-09
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUNICATION
Inventor： LEE KEUN KU , CHOI JIN YOUNG , CHO YOUNG SO , LEE HYEONG HO
IPC: H04J3/12 , H04L12/70 , H04L29/02 , H04M3/36 , H04M3/22 , H04M7/06 , H04Q1/30 , H04Q3/00 , H04Q3/545 , H04Q3/66 , H04L12/56 , H04Q11/04
Abstract: An internal routing method in an internal network for improving signaling message processing capability by balancing the workload among message handling processors (MHP) in common channel signaling system used in electronic exchanges. An internal routing algorithm is provided in the internal network to balance the workload among MHP's based on the characteristics of a circuit identification code (CIC). An identifying trunk circuit is uniformly distributed, and a load unbalancing factor is formulated approximately as a function of the number of failed MHP's as a worst case. With this approach, all MHP's are loaded almost equally regardless of the number of failed MHP's.
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公开(公告)号：FR2714240B1
公开(公告)日：1998-09-04
申请号：FR9415427
申请日：1994-12-21
Inventor： LEE SANG HOON , KO JUNG HOON , LEE TAE HEE , SHIM CHANG SUP
Abstract: Ce dispositif comprend des moyens de sélection 2:1 (8) pour sélectionner l'un de deux signaux d'entrée présentant des écarts temporels, des moyens (28) de production de signaux de sélection, des moyens (9) de production de signaux de commande pour le démultiplexage des données qui ont été sélectionnées, des moyens (10) de démultiplexage pour démultiplexer sous la forme de données à faible vitesse, les données qui ont été sélectionnées, des moyens (12) de multiplexage pour réaliser la synchronisation sur un signal synchrone de trame de référence et un signal d'horloge de référence et multiplexer les données délivrées par les moyens (10) de démultiplexage, et des moyens (11) de production de signaux de référence. Application notamment aux systèmes de transfert numérique de données.
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公开(公告)号：GB2321571A
公开(公告)日：1998-07-29
申请号：GB9723283
申请日：1997-11-05
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUNICATION
Inventor： NAM HONG SOON , KWON YOOL , PARK HONG SHIK
Abstract: An STM-16 Network-Node Interface (NNI) is capable of checking whether a fault is generated on any station when the VC-4 AU received from a remotely located station has the fault, by checking the incoming data streams 17 and communication with the remote node using the still unused values of APS bytes. The interface comprises duplicate physical layer processing blocks 10 for processing a physical layer to provide a plurality of simplex ATM layers, an ATM layer controller 40 for controlling the processing condition of each of the ATM layers processed by the ATM layer processing means, a controlling microprocessor 15; and ATM layer processing block 20 for processing the ATM layers to a plurality of ATM cells.
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Patent Agency Ranking
公开(公告)号：GB2319127A
公开(公告)日：1998-05-13
申请号：GB9720799
申请日：1997-09-30
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN IL SONG , CHOI YOUNG JAE , KIM DAE HWAN
Abstract: Apparatus for converting a voltage into pulses has a charging part 11 receiving the voltage, a voltage comparing part 12 for comparing the output voltage from the charging part 11 with a reference voltage value, a pulse extracting part 13 for outputting pulses in response to the comparison result; and a discharging part 14 for discharging the charge in the charging part 11 in response to the output signal of the pulse extracting part 13 or the comparing part 12.
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公开(公告)号：GB2317726A
公开(公告)日：1998-04-01
申请号：GB9720800
申请日：1997-09-30
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN IL SONG , CHOI YOUNG JAE , KIM DAE HWAN
Abstract: A multiplier and a neural network synapse capable of removing nonlinear current use current mirror circuits The multiplier produces a linear current by using MOS transistors operating in the nonsaturation region. The multiplier comprises a first current mirror M1, M3, M7 to form a first current I 1 and a second current mirror M2, M4, M5 to form a second current I 2 , wherein the second current mirror is coupled in parallel to the first current mirror. The multiplier outputs an output current by subtracting the second current from first current, the output current representing the result of multiplying input voltages V 1 and V 2 . In a neural network synapse the input voltage V 1 is constant and the input voltage V 2 represents the synapse weight. An additional MOS transistor transfers the output current to the load in response to a neural state pulse.
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公开(公告)号：GB9720798D0
公开(公告)日：1997-12-03
申请号：GB9720798
申请日：1997-09-30
Applicant: KOREA TELECOMMUNICATION
Abstract: A multiplier capable of removing nonlinear current using current mirror circuits. The multiplier uses MOSFET and BJT devices by the BiCOMS processes. The multiplier includes three current mirror circuits. A first current mirror includes a BJT Q3 and a BJT Q5 and also the BJT Q3 is coupled in series to the n-channel MOSFET M1 between the voltage V1 and a ground voltage level. A second current mirror includes a BJT Q7 and a BJT Q8. A third current mirror includes a BJT Q4 and a BJT Q6. Consequently, input voltage signals V1 and Vdc applied to the n-channel MOSFETs M1 determine the current I1 and input voltage signals V1 and V2 applied to the n-channel MOSFET M2 determine the current I2.
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公开(公告)号：GB9710775D0
公开(公告)日：1997-07-23
申请号：GB9710775
申请日：1997-05-23
Applicant: KOREA TELECOMMUNICATION
Abstract: A method for automatically verifying the accuracy of an electronic map, said method involving an XORing operation for raster data produced by scanning an original map and vector data finally produced based on the raster data, and a filtering operation for data resulting from the XORing operation. The method includes the steps of scanning an original map, thereby producing raster data, digitizing the raster data, thereby producing vector data, transforming the vector data into raster data, comparing the raster data transformed from the vector data with the original raster data by use of a function of similarity involving an exclusive ORing operation, and removing noise existing in the original raster data by a filtering operation. In accordance with this method, it is possible to reduce the verification time and costs while improving the accuracy of the verification.
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公开(公告)号：GB9710128D0
公开(公告)日：1997-07-09
申请号：GB9710128
申请日：1994-12-14
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUNICATION
IPC: H01L21/762
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