中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.022 seconds)

    METHOD AND APPARATUS FOR ARBITRATION IN A UNIFIED MEMORY ARCHITECTURE
    11.
    发明申请
    METHOD AND APPARATUS FOR ARBITRATION IN A UNIFIED MEMORY ARCHITECTURE 审中-公开
    在统一的存储器架构中进行仲裁的方法和装置

    公开(公告)号：WO0041083A3

    公开(公告)日：2002-05-16

    申请号：PCT/US9930719

    申请日：1999-12-21

    Applicant: INTEL CORP ,  CLOHSET STEVE J ,  DIEP TRUNG A ,  GANDHI WISHWESH ,  PIAZZA THOMAS A ,  SREENIVAS ADITYA ,  TRIEU TUONG P

    Inventor： CLOHSET STEVE J ,  DIEP TRUNG A ,  GANDHI WISHWESH ,  PIAZZA THOMAS A ,  SREENIVAS ADITYA ,  TRIEU TUONG P

    IPC: G06F12/00 ,  G06F12/02 ,  G06F13/18 ,  G06F13/362

    CPC classification number: G06F13/18

    Abstract: According to one embodiment, a computer system is disclosed that includes a memory and a memory controller coupled to the memory. The memory controller includes an arbitration unit that may be programmed to operate according to a first arbitration mode or a second arbitration mode. The computer system also includes a first device and a second device coupled to the arbitration unit. According to a further embodiment, the first device is assigned a higher priority classification than the second device for accessing the memory while the arbitration unit is operating according to the first arbitration mode. In addition, the first device and the second device are assigned equal priority classifications for accessing the memory while the arbitration unit is operating according to the second arbitration mode.

    Abstract translation: 根据一个实施例，公开了一种包括存储器和耦合到存储器的存储器控​​制器的计算机系统。 存储器控制器包括可被编程为根据第一仲裁模式或第二仲裁模式进行操作的仲裁单元。 计算机系统还包括耦合到仲裁单元的第一设备和第二设备。 根据另一实施例，当仲裁单元根据第一仲裁模式操作时，第一设备被分配比用于访问存储器的第二设备更高的优先级分类。 此外，当仲裁单元根据第二仲裁模式操作时，第一设备和第二设备被分配用于访问存储器的相同的优先级分类。

    LOSSY COLOR MERGE FOR MULTI-SAMPLING ANTI-ALIASING COMPRESSION
    12.
    发明申请
    LOSSY COLOR MERGE FOR MULTI-SAMPLING ANTI-ALIASING COMPRESSION 审中-公开
    用于多采样抗锯齿压缩的丢失颜色合成

    公开(公告)号：WO2014189730A1

    公开(公告)日：2014-11-27

    申请号：PCT/US2014/037953

    申请日：2014-05-14

    Applicant: INTEL CORPORATION ,  AKENINE-MOLLER, Tomas G. ,  PIAZZA, Thomas A. ,  SURTI, Prasoonkumar

    Inventor： AKENINE-MOLLER, Tomas G. ,  PIAZZA, Thomas A. ,  SURTI, Prasoonkumar

    IPC: G06T1/00 ,  H04N9/64

    CPC classification number: G06T5/002 ,  G06T9/00 ,  G06T11/40 ,  G06T15/503

    Abstract: Techniques related to graphic rendering including lossy color merge for multi-sampling anti-aliasing compression are discussed. A method for providing anti-aliasing in graphic rendering comprising determining two or more colors associated with a plurality of color samples of a pixel; determining a first color of the two or more colors and a second color of the two or more colors are substantially similar; merging the first color and the second color to form a merged color; and replacing the first color and the second color with the merged color.

    Abstract translation: 讨论了与图形渲染相关的技术，包括用于多采样抗锯齿压缩的有损颜色合并。 一种用于在图形渲染中提供抗锯齿的方法，包括确定与像素的多个颜色样本相关联的两个或多个颜色; 确定两种或更多种颜色的第一颜色和两种或更多种颜色的第二颜色基本相似; 合并第一种颜色和第二种颜色以形成合并的颜色; 并用合并的颜色替换第一颜色和第二颜色。

    TECHNIQUES FOR IMPROVING MSAA RENDERING EFFICIENCY
    13.
    发明申请
    TECHNIQUES FOR IMPROVING MSAA RENDERING EFFICIENCY 审中-公开
    改进MSAA渲染效率的技术

    公开(公告)号：WO2014105609A1

    公开(公告)日：2014-07-03

    申请号：PCT/US2013/076430

    申请日：2013-12-19

    Applicant: INTEL CORPORATION ,  SURTI, Prasoonkumar ,  PIAZZA, Thomas A.

    Inventor： SURTI, Prasoonkumar ,  PIAZZA, Thomas A.

    IPC: G06T15/00 ,  G06T1/20

    CPC classification number: G06T15/503 ,  G06T11/40 ,  G06T15/005 ,  G06T2200/12 ,  G06T2210/08

    Abstract: Various embodiments are generally directed to techniques for causing the storage of a color data value of a clear color to be deferred as rendered color data values are stored for samples. A device comprises a processor circuit and a storage to store instructions that cause the processor circuit to render a pixel from multiple samples taken of a three-dimensional model of an object, the pixel corresponding to a pixel sample data which comprises multiple color storage locations that are each identified by a numeric identifier, and which comprises multiple sample color indices that each correspond to a sample to point to at least one color storage location; and allocate color storage locations in an order selected to define a subset of possible combinations of binary index values among all of the sample color indices as invalid combinations. Other embodiments are described and claimed.

    Abstract translation: 各种实施例通常涉及用于在为样本存储所渲染的颜色数据值时使得清除颜色的颜色数据值的存储被延迟的技术。 一种设备包括处理器电路和存储器，用于存储使得处理器电路从取自对象的三维模型的多个样本渲染像素的指令，该像素对应于包括多个颜色存储位置的像素样本数据， 每个都由数字标识符标识，并且其包括多个样本颜色索引，每个样本颜色索引对应于样本以指向至少一个颜色存储位置; 并且以所选择的顺序分配颜色存储位置，以将所有样本颜色索引中的二进制索引值的可能组合的子集定义为无效组合。 描述和要求保护其他实施例。

    PROCESSING ARCHITECTURE HAVING PASSIVE THREADS AND ACTIVE SEMAPHORES
    15.
    发明申请
    PROCESSING ARCHITECTURE HAVING PASSIVE THREADS AND ACTIVE SEMAPHORES 审中-公开
    具有被动螺纹和主动SEM的加工结构

    公开(公告)号：WO2005066779A1

    公开(公告)日：2005-07-21

    申请号：PCT/US2004/043394

    申请日：2004-12-23

    Applicant: INTEL CORPORATION ,  JIANG, Hong ,  PIAZZA, Thomas, A.

    Inventor： JIANG, Hong ,  PIAZZA, Thomas, A.

    IPC: G06F9/46

    CPC classification number: G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/526

    Abstract: Multiple parallel passive threads of instructions coordinate access to shared resources using “active” semaphores. The semaphores are referred to as active because the semaphores send messages to execution and/or control circuitry to cause the state of a thread to change. A thread can be placed in an inactive state by a thread scheduler in response to an unresolved dependency, which can be indicated by a semaphore. A thread state variable corresponding to the dependency is used to indicate that the thread is in inactive mode. When the dependency is resolved a message is passed to control circuitry causing the dependency variable to be cleared. In response to the cleared dependency variable the thread is placed in an active state. Execution can proceed on the threads in the active state.

    Abstract translation: 指令的多个并行被动线程使用“活动”信号量协调对共享资源的访问。 信号量被称为活动的，因为信号量向执行和/或控制电路发送消息以使得线程的状态改变。 线程调度程序可以响应未解决的依赖关系将线程置于无效状态，这可以由信号量指示。 与依赖关系对应的线程状态变量用于指示线程处于非活动模式。 当依赖关系被解析时，消息被传递给控制电路，导致依赖变量被清除。 响应于清除的依赖变量，线程处于活动状态。 处于活动状态的线程可执行。

    SPATIAL AUGMENTATION OF VERTICES FOR LEVEL OF DETAIL TRANSITION
    16.
    发明专利
    SPATIAL AUGMENTATION OF VERTICES FOR LEVEL OF DETAIL TRANSITION 未知

    公开(公告)号：CA2020550A1

    公开(公告)日：1991-01-11

    申请号：CA2020550

    申请日：1990-07-05

    Applicant: PIAZZA THOMAS A ,  ECONOMY RICHARD ,  PELHAM ANTHONY J ,  QUICK LEE T

    Inventor： PIAZZA THOMAS A ,  ECONOMY RICHARD ,  PELHAM ANTHONY J ,  QUICK LEE T

    IPC: G06T15/50 ,  G09G5/00

    Abstract: In a computer image generation system, the number of vertices which define polygons is augmented in real time for providing finer detail and for effecting smooth level of detail transition. Augmented vertices may have components that are statistically derived in which case it is not necessary to store and/or predefine them. Alternatively, some vertex components may have predetermined values derived from mapping data or from other deterministic sources and may be stored in compact form. Processing polygons defined by the augmented vertices along with the original vertices may be used for displaying the finer detail. Statistically derived finer detail is especially suited for providing non-specific detail to features such as terrain and bodies of water, while deterministic data allows highly accurate representations of specific 'real world' locations. Vertex augmentation may be controlled by the following breakupcriteria: range from the viewpoint, angle from the viewpoint boresight, desired maximum error or other criteria and combinations thereof.

Patent Agency Ranking