公开(公告)号：US08748291B2

公开(公告)日：2014-06-10

申请号：US13629157

申请日：2012-09-27

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Ltd (Malta)

Inventor： Mark Anthony Azzopardi ,  Conrad Cachia ,  Stefano Pozzi

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: B81C99/004 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for testing a strip of MEMS devices, the MEMS devices including at least a respective die of semiconductor material coupled to an internal surface of a common substrate and covered by a protection material; the method envisages: detecting electrical values generated by the MEMS devices in response to at least a testing stimulus; and, before the step of detecting, at least partially separating contiguous MEMS devices in the strip. The step of separating includes defining a separation trench between the contiguous MEMS devices, the separation trench extending through the whole thickness of the protection material and through a surface portion of the substrate, starting from the internal surface of the substrate.

Abstract translation: 一种用于测试MEMS器件条的方法，所述MEMS器件至少包括耦合到公共衬底的内表面并由保护材料覆盖的半导体材料的相应裸片; 该方法设想：响应于至少一个测试刺激来检测由MEMS器件产生的电值; 并且在所述检测步骤之前，至少部分地分离所述条带中的连续的MEMS器件。 分离步骤包括在连续的MEMS器件之间限定分离沟槽，分离沟槽从衬底的内表面开始延伸穿过保护材料的整个厚度并穿过衬底的表面部分。

公开(公告)号：US20130032936A1

公开(公告)日：2013-02-07

申请号：US13648213

申请日：2012-10-09

Applicant: STMICROELECTRONICS LTD (MALTA)

Inventor： Kevin Formosa

IPC: H01L23/12 ,  H01L21/50

CPC classification number: B81B7/0074 ,  B81B7/0061 ,  B81B2201/0257 ,  B81B2207/012 ,  B81C1/00309 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/4824 ,  H04R19/005 ,  H04R19/04 ,  H04R31/00 ,  H04R2201/003 ,  H01L2924/00014

Abstract: A packaged MEMS device, wherein at least two support structures are stacked on each other and are formed both by a support layer and a wall layer coupled to each other and delimiting a respective chamber. The chamber of the first support structure is upwardly delimited by the support layer of the second support structure. A first and a second dice are accommodated in a respective chamber, carried by the respective support layer of the first support structure. The support layer of the second support structure has a through hole allowing wire connections to directly couple the first and the second dice. A lid substrate, coupled to the second support structure, closes the chamber of the second support structure.

Abstract translation: 一种封装的MEMS器件，其中至少两个支撑结构彼此堆叠并且由支撑层和彼此耦合并限定相应室的壁层形成。 第一支撑结构的腔室由第二支撑结构的支撑层向上限定。 第一和第二骰子容纳在由第一支撑结构的相应支撑层承载的相应的腔室中。 第二支撑结构的支撑层具有允许电线连接直接耦合第一和第二裸片的通孔。 耦合到第二支撑结构的盖基板封闭第二支撑结构的室。

公开(公告)号：US08921164B2

公开(公告)日：2014-12-30

申请号：US13772210

申请日：2013-02-20

Applicant: STMicroelectronics Ltd (Malta) ,  STMicroelectronics S.r.l.

Inventor： Kenneth Fonk ,  Luca Maggi ,  Jeremy Spiteri

IPC: H01L21/00 ,  H01L23/495

CPC classification number: B81B7/0045 ,  B81B2201/0264 ,  B81B2207/012 ,  B81C1/00238 ,  B81C1/00325 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A process for assembly of an integrated device, envisages: providing a first body of semiconductor material integrating at least one electronic circuit and having a top surface; providing a second body of semiconductor material integrating at least one microelectromechanical structure and having a bottom surface; and stacking the second body on the first body with the interposition, between the top surface of the first body and the bottom surface of the second body, of an elastic spacer material. Prior to the stacking step, the step is envisaged of providing, in an integrated manner, at the top surface of the first body a confinement and spacing structure that confines inside it the elastic spacer material and supports the second body at a distance from the first body during the stacking step.

Abstract translation: 集成装置的组装方法设想：提供集成至少一个电子电路并具有顶表面的第一半导体材料体; 提供集成至少一个微机电结构并具有底表面的第二半导体材料; 并且在所述第一主体的顶表面和所述第二主体的所述底表面之间插入所述第一主体上的所述第二主体的弹性间隔件材料。 在层叠步骤之前，该步骤被设想为以第一体积的方式在第一体的顶表面处提供约束和间隔结构，该限制和间隔结构在其内部限定弹性间隔物材料，并且将第二体与第一体 身体在堆叠步骤。

公开(公告)号：EP2149901A1

公开(公告)日：2010-02-03

申请号：EP09167061.2

申请日：2009-08-03

Applicant: STMicroelectronics Ltd (Malta)

Inventor： Mifsud, Anthony Mario

IPC: H01L23/60 ,  H01L23/31 ,  H01L23/485

CPC classification number: H01L23/60 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Method for manufacturing an electronic device realised on a semiconductor substrate (22, 32) and protected against Electro Static Discharge by the provision of supporting means (24, 34) for the electronic device to keep it far from contacts with possible sources of an ESD event during the manufacturing phases. The supporting means (24, 34) are associated to said electronic device in all the manufacturing stages for instance when assembling the device; when picking and placing it in trays a first time; during the burning-in testing phases, when picking and placing it in trays a second time, or when picking and placing it in a scanner.
In particular, the supporting means (24, 34) are protective notches (24; 34) associated to the back side of the semiconductor substrate (22; 32) and provided at each edge corner of the semiconductor substrate (22;32).

Abstract translation: 制造由用于电子设备提供支撑装置（24，34）来实现在半导体基板（22，32）和防静电放电保护的电子设备的方法，以从与ESD事件的可能来源的联络人保持它远 在制造阶段。 所述支撑装置（24，34）被关联到所述电子设备中的所有制造阶段例如当组装装置; 当拾取和放置它在第一次盘; 在刻录机测试阶段，当选择并把它放在托盘第二次，或当拾取和放置它的扫描仪。 （24; 34）特别是，该支撑装置（24，34）是关联到所述半导体基板的背面保护凹口（22; 32），并在半导体衬底（22; 32）的每个边缘角提供。

公开(公告)号：EP1878692B1

公开(公告)日：2011-04-20

申请号：EP06014651.1

申请日：2006-07-14

Applicant: STMicroelectronics Srl ,  STMicroelectronics Ltd (Malta)

Inventor： Ziglioli, Federico Giovanni ,  Graziosi, Giovanni ,  Shaw, Mark Andrew ,  Cortese, Mario Francesco ,  Cachia, Conrad Max

IPC: B81B7/00 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81B7/0048 ,  B81B2207/096 ,  B81C2203/0154 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2272794A1

公开(公告)日：2011-01-12

申请号：EP10184071.8

申请日：2006-07-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Ltd (Malta)

Inventor： Ziglioli, Federico Giovanni ,  Graziosi, Giovanni ,  Shaw, Mark Andrew ,  Cortese, Mario Francesco ,  Cachia, Conrad Max

IPC: B81B7/00 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81B7/0048 ,  B81B2207/096 ,  B81C2203/0154 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package comprising a substrate (20) and a damage-sensitive device (21), comprising a package substrate core (14) having an upper and a lower surface (14a, 14b), at least one pair of metal layers (12a, 12b, 13a, 13b) coating said upper and lower surfaces (14a, 14b) of the package substrate core (14); one pair of solder mask layers (11a, 11b) coating the outer metal layers (12a, 12b) of the at least one pair of metal layers (12a, 12b, 13a, 13b); and a plurality of vias (19) formed across the package substrate core (14) and the at least one pair of metal layers (12a, 12b, 13a, 13b) and a damage-sensitive device mounted on top of the upper solder mask layer. Advantageously, the plurality of vias (19) is substantially distributed according to a homogeneous pattern in an area (21 a) that is to be covered by the damage-sensitive device (21), a plurality of vias (19) being positioned so that the vias substantially coincide with an outline of said damage-sensitive device (21) that the semiconductor package substrate (20) is intended to support.
A method for the production of such semiconductor package substrate is also described.

Abstract translation: 一种包括基板（20）和损伤敏感装置（21）的半导体封装，包括具有上表面和下表面（14a，14b）的封装衬底芯（14），至少一对金属层（12a， 12b，13a，13b）涂覆所述封装基板芯（14）的所述上表面和下表面（14a，14b）; 一对涂覆至少一对金属层（12a，12b，13a，13b）的外金属层（12a，12b）的焊料掩模层（11a，11b） 以及形成在所述封装衬底芯（14）和所述至少一对金属层（12a，12b，13a，13b）之间的多个通孔（19）和安装在所述上焊接掩模层的顶部上的损伤敏感器件 。 有利地，多个通孔（19）根据待被损伤敏感设备（21）覆盖的区域（21a）中的均匀图案基本上分布，多个通孔（19）被定位成使得 通孔基本上与半导体封装衬底（20）旨在支撑的所述损伤敏感器件（21）的轮廓一致。 还描述了制造这种半导体封装基板的方法。

公开(公告)号：EP1884981A1

公开(公告)日：2008-02-06

申请号：EP06118420.6

申请日：2006-08-03

Applicant: STMicroelectronics Ltd (Malta)

Inventor： Formosa, Kevin

IPC: H01L21/00 ,  H01L21/68 ,  H01L21/78

CPC classification number: H01L21/6835 ,  H01L21/67132 ,  H01L21/67144 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/68336

Abstract: The present invention relates to a removable wafer expander for a die bonding equipment for singularized wafer (7) supported by flexible sticky means (8). Said removable wafer expander is provided with a first ring member (2) to be coupled with a second ring member (3) for a remote expansion of said flexible sticky means (8) comprises therebetween before the mounting of said wafer expander onto the die bonding equipment.

Abstract translation: 本发明涉及用于由柔性粘性装置（8）支撑的单晶化晶片（7）的晶片键合设备的可移除晶片扩展器。 所述可移除晶片扩展器设置有第一环构件（2），所述第一环构件与第二环构件（3）耦合，用于在所述晶片扩展器安装到管芯接合之前，所述柔性粘性构件（8）包括其间的远程扩展 设备。

公开(公告)号：EP1878692A1

公开(公告)日：2008-01-16

申请号：EP06014651.1

申请日：2006-07-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Ltd (Malta)

Inventor： Ziglioli, Federico Giovanni ,  Graziosi, Giovanni ,  Shaw, Mark Andrew ,  Cortese, Mario Francesco ,  Cachia, Conrad Max

IPC: B81B7/00 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81B7/0048 ,  B81B2207/096 ,  B81C2203/0154 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package substrate (20) suitable for supporting a damage-sensitive device (21), comprising a package substrate core (14) having an upper and a lower surface (14a, 14b), at least one pair of metal layers (12a, 12b, 13a, 13b) coating said upper and lower surfaces (14a, 14b) of the package substrate core (14); one pair of solder mask layers (11a, 11b) coating the outer metal layers (12a, 12b) of the at least one pair of metal layers (12a, 12b, 13a, 13b); and a plurality of vias (19) formed across the package substrate core (14) and the at least one pair of metal layers (12a, 12b, 13a, 13b). Advantageously, the plurality of vias (19) is substantially distributed according to a homogeneous pattern in an area (21a) that is to be covered by the damage-sensitive device (21).
A method for the production of such semiconductor package substrate is also described.

Abstract translation: 一种适于支撑损伤敏感器件（21）的半导体封装衬底（20），包括具有上表面和下表面（14a，14b）的封装衬底芯（14），至少一对金属层（12a， 12b，13a，13b）涂覆所述封装基板芯（14）的所述上表面和下表面（14a，14b）; 一对涂覆至少一对金属层（12a，12b，13a，13b）的外金属层（12a，12b）的焊料掩模层（11a，11b） 以及形成在所述封装衬底芯（14）和所述至少一对金属层（12a，12b，13a，13b）之间的多个通孔（19）。 有利的是，多个通孔（19）在要被损伤敏感装置（21）覆盖的区域（21a）中根据均匀的图案基本分布。 还描述了制造这种半导体封装基板的方法。