公开(公告)号：JPH0851356A

公开(公告)日：1996-02-20

申请号：JP9522195

申请日：1995-04-20

Applicant: XILINX INC

Inventor： RANDEII TEII ONGU

IPC: H03K19/173 ,  H03K19/177

Abstract: PURPOSE: To increase the number of realizable logical functions by internally configuring a CLB (logical block) and a configurable routing matrix again and executing the plural pieces of the logical functions. CONSTITUTION: A configuration memory 16 is provided with memory cells 21-1 to 21-n and 23-1 to 23-n and switches 28-1 to 48-n. The memories 21 and 23 store the complete set of configuration data CFD for the CLB and the configurable routing matrix CRM. The CLB and CRM use one of the CFD stored in the memories 21 and 23 and specify a form. The switches 28 pass through signals in response to selection input from an A/B line 30 and supply them to the CLB and the CRM. Thus, the CLB and the CRM are configured again, that is form-specified, corresponding to the two alternative set of the CFD.

公开(公告)号：JPH088758A

公开(公告)日：1996-01-12

申请号：JP2437992

申请日：1992-01-16

Applicant: XILINX INC

Inventor： CHIYAARUZU AARU ERIKUSON ,  FUIRITSUPU EMU FUREIDEIN

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/09 ,  H04L1/00

Abstract: PURPOSE: To detect an error with high reliability with a few inspection bits by dividing a data stream into frames, adding the sub-set of error check words to the end of each frame, and forming a transmission frame. CONSTITUTION: A transmission block is generated at a transmission position by dividing the data stream of one transmission session into data frames, generating and updating check words being the function of the bits of the whole data stream, and adding the sub-set of the check words to the end of each data frame. The data frame is divided into N frames 1 to n and sub-sets CW 1-CWn of the check words are inserted into the end of each home. Then, the sub-set CWn of the check words longer than the other subsets is added to the end of the final frame (n). A pattern for periodically inserting the sub-sets of the check words into the data stream can be selected in various ways as long as the same pattern is used at the both edges of transmission.

公开(公告)号：JPH07147303A

公开(公告)日：1995-06-06

申请号：JP15180094

申请日：1994-06-10

Applicant: XILINX INC

Inventor： SHIERUDON OO RAASON ,  RONARUDO JIEI MATSUKU

IPC: G01R31/26 ,  G06F11/22 ,  H01L21/66 ,  H01L23/544

Abstract: PURPOSE: To reduce the testing time of a die on a wafer by allowing a file created for a wafer on which a qualitative die is positioned to store each position of the quality die, performing access to the prescribed memory cell of the die, deciding the related file of the die, and testing the quality die of the wafer. CONSTITUTION: A die which has been decided as a quality die (all memory cells indicate a proper threshold voltage) is printed electrically. The prescribed memory cell of each qualitative die called an 'identfication(ID) cell' is programmed, so that a file related with a specific wafer can be identified. The position of each quality die on the wafer is stored in the file related to the wafer. All the wafers are placed under a prescribed adverse condition, and the radiation of the memory cells of the wafer is accelerated. The ID cell of the electrically printed first die of the wafer is read. After the first position in the file has been read, this process is allowed to proceed directly to the first 'qualitaty' die decided by a first wafer sort 400 of the wafer.

公开(公告)号：JPH0737984A

公开(公告)日：1995-02-07

申请号：JP34819491

申请日：1991-12-04

Applicant: XILINX INC

Inventor： EFU ERITSUKU GOUCHINGU ,  DEBITSUTO BII PAARAA ,  JIYON II MAHOONII

IPC: G01R31/317 ,  G11C17/18 ,  H01L21/82 ,  H03K19/177

Abstract: PURPOSE: To connect logic devices via line segments capable of being coupled according to programs of anti-fuses. CONSTITUTION: Program lines VP0-VP3 are connected to terminals of anti-fuses F1 in an array through connection line segments one to one. The line segments connected to both terminals of one anti-fuse are connected to different program lines, because different voltages are applied to two terminals of the anti-fuse. An addressing structure selectively connects the line segments respectively to the program lines and programs the selected anti-fuse with a programming voltage applied to the programming line. It has an addressing characteristic which addresses, about the line segments to be connected, two transistors one after the other and keeps the addressed transistors T51, T52 set on, utilizing capacitive pump decoders D51, D52.

公开(公告)号：JPH0645912A

公开(公告)日：1994-02-18

申请号：JP29052891

申请日：1991-10-09

Applicant: XILINX INC

Inventor： UIRIAMU ESU KAATAA

IPC: G11C19/28 ,  H03K3/037 ,  H03K5/1534 ,  H03K19/173

Abstract: PURPOSE: To configure a configurable logic element which realizes extremely diversified functions. CONSTITUTION: A combination logic circuit receives N-sets of binary input signals, fed to a configurable logic element 99 and M-sets of binary feedback signals from a storage circuit 120. A combination logic circuit 100 is configured to have a plurality of configurations. Each configuration realizes one or a plurality of selected combination logic functions as partial sets, which is selected from one or a plurality of input signals to the combination logic circuit. Since the combination logic circuit 100 is configurable, the circuit 100 is used to realize a plurality of different functions. Furthermore, two functions or over are realized simultaneously, and they can be made to appeared on different output leads of the configurable logic element 100.

公开(公告)号：JPH04223715A

公开(公告)日：1992-08-13

申请号：JP8789491

申请日：1991-03-27

Applicant: XILINX INC

Inventor： ROSU EICHI FURIIMAN ,  KIYUU DOUONGU ,  HANGUUCHIENGU SHII ,  CHIYAARUZU AARU ERIKUSON ,  UIRIAMU ESU KAATAA

IPC: G06F3/00 ,  H01L21/82 ,  H03K19/173

Abstract: PURPOSE: To provide a structure effective for a configurable logic array having plural conductive connecting lines around it to prevent the speed of information processing from being decelerated and valuable resources inside a chip usable for executing a complicated function from being used. CONSTITUTION: A line running from a pin or a pad outside a programmable connection circuit is used for controlling a signal to be impressed to the connecting line. Concerning this signal and its complement, the application of a voltage to be supplied to the connecting line is controlled while using a programmable connection part. When the 2nd supply voltage is applied through a resistor to the connecting line, the connecting line transmits a logic signal expressing the logic function such as AND, for example, of the set of selected input signals or their complements. Besides, a line inside a configurable logic array chip is effective for a signal generated on the connecting line. Because of a bidirectional programmable connection circuit, an input pin can be functioned as the input pin or as an output pin. This structure can be used as the latch of a data/address demultiplexer and applied to a decoder circuit.

公开(公告)号：JPH03183154A

公开(公告)日：1991-08-09

申请号：JP12323390

申请日：1990-05-15

Applicant: XILINX INC

Inventor： JIYON II MAHONEE

IPC: G01R31/317 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G06F17/50 ,  H01L21/82 ,  H01L23/528 ,  H01L27/118

Abstract: PURPOSE: To provide a logical cell array device with which the designer of an application specific integrated circuits (ASIC's) can relatively easily change the design of the integrated circuit from a user's type to a mask type by constituting an integrated circuit chip interconnected through through a metal can become pin-compatible with an integrated circuit chip interconnected through a path transistor. CONSTITUTION: A logical cell array device (LCA) 10 is provided with many predesigned logical function blocks (LFB's) 12 and the LFB's 12 are distributed across the surface of an integrated circuit board 13 in accordance with a predetermined distribution pattern. The LFB's 12 have various digital logical functions and the property of a fixed table of truth value (hard-wired combinational logic circuit) or such a property that can be constituted internally (can be soft- wired). Field effect path transistors 14a, 14b, 14c,..., 14j which can be operated in programmable states are contained in the interconnected matrix 14 of the LCA 10 and programmably connect various input and output terminals of the LFB's 12 to each other.

公开(公告)号：JPH0290075A

公开(公告)日：1990-03-29

申请号：JP25217988

申请日：1988-10-07

Applicant: XILINX INC

Inventor： JIYON II MAHONII

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/22

Abstract: PURPOSE: To make it possible to execute a new scan test for logic circuit network by providing a scan test system with a main test circuit integrated with at least one logic test block. CONSTITUTION: In the scan test system for a logic circuit, multiple circuits for logic signal process where each circuit has an input line and an output line and multiple logic test blocks which mutually connects these circuits are contained. The logic test block is inserted in each main circuit line at the place where validation of logic signal is desired. In addition, a scan in terminal and a scan out terminal of the logic test block are connected each other so that a shift register is formed. Then, a means which connects a circuit output line of one of multiple circuits to a circuit input line of the other of multiple circuits is separated from a shift register stage during normal operation, and the shift register stage effectively functions for a test of the multiple circuits.

公开(公告)号：JPH021565A

公开(公告)日：1990-01-05

申请号：JP28231388

申请日：1988-11-08

Applicant: XILINX INC

Inventor： HANGU CHIENGU SHII

IPC: G01R31/319 ,  G01R19/165 ,  H03K17/22 ,  H03K17/30

Abstract: PURPOSE: To detect the voltage level at the time of power supply starting time and voltage drop by generating a reset signal for sustaining an element in an integrated circuit including a power supply voltage level detection circuit in a defined state when the power supply voltage level drops below a predetermined level. CONSTITUTION: Trigger points of inverters 60, 70 are crossed at a predetermined voltage. When the output signal from inverter 60 is fed to the input terminal of inverter 70, output signal from the inverter 70 has a first level if the power supply voltage level is higher than a predetermined level otherwise has a second level. The inverter changes the state even when the power supply voltage level drops below the predetermined level instantaneously. A filter is connected with the output terminal of inverter 70 in order to prevent the circuit from being reset due to instantaneous power supply voltage drop.

公开(公告)号：JPH0540804A

公开(公告)日：1993-02-19

申请号：JP32514291

申请日：1991-11-13

Applicant: XILINX INC

Inventor： SUCHIIBUN JIEI PERII

IPC: H01L21/82 ,  G06F17/50 ,  H01L27/02

Abstract: PURPOSE: To automatically lay out electronic circuit components, i.e., constituting elements in the surface regions of a circuit supporting board. CONSTITUTION: The logical design consists of symbol natation indicating many source function elements including plural wirings W1, W2,... so as to connect the input and output terminals of 1st AND gates E1, 10th gates E2, 3-state buffers E3, 20th R gates E4, 2nd AND gates E5, 30th R gates E6, flip-flops E7 to each other and connecting these terminals to other logic elements, E10, etc. The logical design is provided with coordinates for mapping indicating the regions of vertical columns by A, B, etc., and horizontal rows by 1, 2, etc. The function elements E1 to E7 are fitted into the self-divided regions A1. Other structures, for example, E100 and E101 are dispersed irregularly in the regions of C4. The logical design starts from irregularly collecting such function elements as shown in the regions C4 and is rearranged in the logical sense reverse from a physical sense until the elements are considered to be orderly arranged in the regions A1.