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公开(公告)号：KR1020050055805A
公开(公告)日：2005-06-14
申请号：KR1020030088825
申请日：2003-12-09
Applicant: 삼성전자주식회사
IPC: H01L21/66
Abstract: 크랙을 검출하기 위해 테스트 커맨드(test command)에 따라 제 1 레벨을 가지는 기준 신호가 발생된다. 제 2 레벨을 가지는 라인 신호가 반도체 칩에 형성된 라인 패스를 통해 패스된 1 레벨을 가지는 기준 신호를 이용함에 의해 발생된다. 상기 라인 신호는 상기 기준 신호와 비교된다. 그 결과, 상기 크랙의 발생에 대한 정보를 가지는 크랙 검출 신호가 발생된다. 반도체 칩이 상기 칩의 테두리를 따라 형성된 라인 패스를 포함하므로, 미세한 크랙이 정확하게 검출된다.
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公开(公告)号：KR1020040095096A
公开(公告)日：2004-11-12
申请号：KR1020030028702
申请日：2003-05-06
Applicant: 삼성전자주식회사
IPC: G11C7/10
Abstract: PURPOSE: A memory system and a semiconductor memory device are provided to stabilize the data transmitted/received through the bus line by utilizing the termination voltage as a reference voltage required for the input circuit of the semiconductor device. CONSTITUTION: A memory system includes a memory controller(310) and a plurality of memory devices(320,330,340,350). The termination resistors of the memory bus lines are incorporated into the memory controller(310) and the plurality of memory devices(320,330,340,350). The memory system is characterized in that the termination voltage of the memory bus line is utilized as the reference voltage applied to the input circuit of the memory controller(310) and the plurality of memory devices(320,330,340,350).
Abstract translation: 目的：提供存储器系统和半导体存储器件，以通过利用终端电压作为半导体器件的输入电路所需的参考电压来稳定通过总线发送/接收的数据。 构成：存储器系统包括存储器控制器（310）和多个存储器件（320,330,340,350）。 存储器总线的终端电阻被并入到存储器控制器（310）和多个存储器件（320,330,340,350）中。 存储器系统的特征在于，利用存储器总线的终端电压作为施加到存储器控制器（310）和多个存储器件（320,330,340,350）的输入电路的参考电压。
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公开(公告)号：KR1020040039617A
公开(公告)日：2004-05-12
申请号：KR1020020067745
申请日：2002-11-04
Applicant: 삼성전자주식회사
Inventor： 김정열
IPC: G11C11/40
CPC classification number: H03K19/018521 , H03K19/00384
Abstract: PURPOSE: An output buffer circuit capable of reducing skew of output data is provided to reduce skew of output data even though PVT(Process, Voltage, Temperature) is changed. CONSTITUTION: A pull-up transistor(31) pulls up an output port in response to a pull-up control signal. A pull-down transistor(33) pulls down the output port in response to a pull-down control signal. A NAND gate(35) generates the pull-up control signal by receiving at least one control signal and data. And a NOR gate(37) generates the pull-down control signal by receiving an inverted signal of the control signal and the data. The number of PMOS transistors on a path from the first power supply voltage to an output port of the NAND gate is the same as the number of PMOS transistors on a path from the first power supply voltage to an output port of the NOR gate. The number of NMOS transistors on a path from the output port of the NAND gate to the second power supply voltage is the same as the number of NMOS transistors on a path from the output port of the NOR gate to the second power supply voltage.
Abstract translation: 目的：提供能够减少输出数据偏移的输出缓冲电路，以减少输出数据的偏移，即使PVT（过程，电压，温度）发生变化。 构成：上拉晶体管（31）响应于上拉控制信号上拉输出端口。 下拉晶体管（33）响应于下拉控制信号而拉出输出端口。 NAND门（35）通过接收至少一个控制信号和数据来产生上拉控制信号。 而NOR门（37）通过接收控制信号和数据的反相信号来产生下拉控制信号。 从第一电源电压到NAND门的输出端口的路径上的PMOS晶体管的数量与从第一电源电压到或非门的输出端口的路径上的PMOS晶体管的数量相同。 从NAND门的输出端口到第二电源电压的路径上的NMOS晶体管的数量与从NOR门的输出端口到第二电源电压的路径上的NMOS晶体管的数量相同。
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公开(公告)号：KR1020040011958A
公开(公告)日：2004-02-11
申请号：KR1020020045287
申请日：2002-07-31
Applicant: 삼성전자주식회사
IPC: G11C11/40
CPC classification number: G11C7/1066 , G11C7/1012 , G11C7/1039 , G11C7/1051 , G11C7/1072
Abstract: PURPOSE: A data output circuit of a synchronous semiconductor memory device is provided to minimize junction loading and interconnection loading and data skew. CONSTITUTION: According to the data output circuit of a synchronous semiconductor memory device comprising a data output multiplexer having a wave pipeline structure, every output port of two register output selection switches is connected to a multiplexing output line through a single line, by forming output part active regions of adjacent register output selection switches(S1,S2,S3,S4,S5,S8,S9,S10,S12,S13,S16) in common, in order to reduce junction loading of the multiplexing output line connected to lines connected to output ports of register output selection switches in the above data output multiplexer in common. The above register output selection switches are constituted with a CMOS transmission gate respectively.
Abstract translation: 目的：提供同步半导体存储器件的数据输出电路以最小化负载和互连负载以及数据偏移。 构成：根据包括具有波形流水线结构的数据输出多路复用器的同步半导体存储器件的数据输出电路，两个寄存器输出选择开关的每个输出端口通过一条线连接到复用输出线，通过形成输出部分 相邻寄存器输出选择开关（S1，S2，S3，S4，S5，S8，S9，S10，S12，S13，S16）的有源区域是为了减少与连接到 上述数据输出多路复用器中的寄存器输出选择开关的输出端口是共同的。 上述寄存器输出选择开关分别由CMOS传输门构成。
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公开(公告)号：KR1020040000147A
公开(公告)日：2004-01-03
申请号：KR1020020035303
申请日：2002-06-24
Applicant: 삼성전자주식회사
IPC: G11C7/06
Abstract: PURPOSE: A load transistor circuit having a variable amplitude to supply a stable current and a stable voltage to an amplification circuit is provided to vary a current level selectively by supplying a constant and stable current. CONSTITUTION: According to the load transistor circuit(210) which is a current source of an amplification circuit(120), the first and the second line are connected to the amplification circuit to sense and amplify its data value. The first driver part(212) is connected between a power supply voltage(VDD) and the first line and provides the first supply current to the amplification circuit in response to a load enable signal(LEN). And the second driver part(214) is connected between the power supply voltage and the second line and provides the second supply current to the amplification circuit in response to the load enable signal and a control signal(CTRL).
Abstract translation: 目的：提供具有可变幅度以向放大电路提供稳定电流和稳定电压的负载晶体管电路，以通过提供恒定和稳定的电流来选择性地改变电流电平。 构成：根据作为放大电路（120）的电流源的负载晶体管电路（210），第一和第二线路连接到放大电路以检测和放大其数据值。 第一驱动器部分（212）连接在电源电压（VDD）和第一线之间，并响应于负载使能信号（LEN）而向放大电路提供第一电源电流。 并且第二驱动器部分（214）连接在电源电压和第二线之间，并且响应于负载使能信号和控制信号（CTRL）将第二电源电流提供给放大电路。
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Patent Agency Ranking
公开(公告)号：KR1019900007383B1
公开(公告)日：1990-10-08
申请号：KR1019880006536
申请日：1988-05-31
Applicant: 삼성전자주식회사
Inventor： 김정열
CPC classification number: H05B6/06 , Y10S323/902
Abstract: An output control circuit of combining a time on-off control method with a freq. control method comprises a current transformer (12), a rectifier (13), an inverter (18) for providing a voltage to a heating coil, an output controller (20) including a pulse width modulation circuit and a current feedback/output control circuit, an output setting controller (23) including a number of photo-couplers, a decoder and a microprocessor for providing a predetermined output, a base driver (19) for controlling the inverter, a timing circuit (22) for providing a pulse with a predetermined time constant, and a triangular wave generator (24) for providing a triangular wave corresponding to a pulse period of the timing circuit.
Abstract translation: 一种将时间开关控制方法与频率组合的输出控制电路。 控制方法包括电流互感器（12），整流器（13），用于向加热线圈提供电压的逆变器（18），输出控制器（20），包括脉宽调制电路和电流反馈/输出控制电路 ，包括多个光耦合器，解码器和用于提供预定输出的微处理器的输出设置控制器（23），用于控制逆变器的基本驱动器（19），用于提供脉冲的定时电路（22） 以及用于提供与定时电路的脉冲周期对应的三角波的三角波发生器（24）。
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