中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.021 seconds)

    반도체 장치 및 그 제조 방법
    12.
    发明授权
    반도체 장치 및 그 제조 방법 有权

    公开(公告)号：KR101923946B1

    公开(公告)日：2018-11-30

    申请号：KR1020120096620

    申请日：2012-08-31

    Applicant: 삼성전자주식회사

    Inventor： 유청식 ,  배철휘 ,  김주연 ,  홍창민

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238

    CPC classification number: H01L27/1104 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/1116

    Abstract: 반도체장치가제공된다. 반도체장치는, 제1 및제2 영역을포함하는반도체기판, 제1 영역상에형성된제1 고유전율막패턴, 제2 영역상에형성되고상기제1 고유전율막패턴과동일한두께를갖는제2 고유전율막패턴, 제1 고유전율막패턴상에형성되고제1 두께를갖는제1 일함수조절막패턴, 제1 일함수조절막패턴상에형성되고제2 두께를갖는제2 일함수조절막패턴, 제2 고유전율막패턴상에형성되고제1 두께보다작은제3 두께를가지며, 제1 일함수조절막패턴과동일한물질로이루어진제3 일함수조절막패턴, 및제3 일함수조절막패턴상에형성되고제2 두께보다큰 제4 두께를가지며, 제2 일함수조절막패턴과동일한물질로이루어진제4 일함수조절막패턴을포함한다.

    반도체 플러그를 공유콘택 구조체로 채택하는 반도체 소자및 그의 제조방법들
    14.
    发明公开
    반도체 플러그를 공유콘택 구조체로 채택하는 반도체 소자및 그의 제조방법들 无效
    使用半导体插片作为共享接触结构的半导体器件及其制造方法

    公开(公告)号：KR1020080076509A

    公开(公告)日：2008-08-20

    申请号：KR1020070016526

    申请日：2007-02-16

    Applicant: 삼성전자주식회사

    Inventor： 진유승 ,  배철휘

    IPC: H01L21/8244 ,  H01L21/28

    Abstract: A semiconductor device employing a semiconductor plug as a shared contact structure and fabricating method thereof are provided to prevent flow of leakage current through a junction of low concentration node impurity region in case of applying reverse bias is applied between a shared semiconductor plug and a semiconductor substrate. A semiconductor device employing a semiconductor plug as a shared contact structure comprises gate electrodes(120t',120t"), node impurity regions(125a,125b), a shared semiconductor plug(140), and metal silicide layers(150). The gate electrode is formed on a semiconductor substrate(105). The node impurity region is formed adjacent to the gate electrode in the semiconductor substrate. The shared semiconductor plug covers a first region of the gate electrode and the node impurity region near the first region, connecting the gate electrode with the node impurity electrode electrically. The metal silicide layer is formed on the gate electrode, the surface of the shared semiconductor plug, and the surface of the node impurity region. The shared semiconductor plug is formed through a selective epitaxial growth.

    Abstract translation: 提供采用半导体插头作为共用接触结构的半导体器件及其制造方法，以防止在共享半导体插头和半导体衬底之间施加反向偏压的情况下通过低浓度节点杂质区域的接合点的漏电流 。 采用半导体插头作为共享接触结构的半导体器件包括栅电极（120t'，120t“），节点杂质区（125a，125b），共用半导体插头（140）和金属硅化物层（150） 电极形成在半导体衬底（105）上，在半导体衬底中与栅电极相邻形成节点杂质区域，共享半导体插头覆盖栅电极的第一区域和第一区域附近的节点杂质区域，连接 栅电极与节点杂质电极电连接，金属硅化物层形成在栅电极，共用半导体插头的表面和节点杂质区的表面上，通过选择性外延生长形成共用半导体插头。

    테스트 패턴 및 이를 이용한 결함 모니터링 방법
    15.
    发明授权
    테스트 패턴 및 이를 이용한 결함 모니터링 방법 失效
    测试模式和使用该方法监测缺陷的方法

    公开(公告)号：KR100761763B1

    公开(公告)日：2007-09-28

    申请号：KR1020060087559

    申请日：2006-09-11

    Applicant: 삼성전자주식회사

    Inventor： 이혁준 ,  배철휘 ,  박영렬 ,  이남영 ,  이미정

    IPC: H01L21/66

    CPC classification number: G01R31/2884 ,  H01L22/34

    Abstract: A test pattern and a method for monitoring defects using the same are provided to apply both contact and non-contact manners to one test pattern by using a conductive line electrically connected to a normal pattern and electrically isolated from an abnormal pattern. A test pattern includes a normal pattern(110), an abnormal pattern(120) having a defect, and a conductive line(130) electrically connected to the normal pattern and electrically isolated from the abnormal pattern. The normal pattern has first patterns(112) electrically connected to the conductive line and second patterns(114) arranged between the first patterns. The second patterns are connected to a ground(150).

    Abstract translation: 提供一种用于监测使用其的缺陷的测试图案和方法，以通过使用与正常图案电连接并与异常图案电隔离的导电线将接触和非接触方式应用于一个测试图案。 测试图案包括正常图案（110），具有缺陷的异常图案（120）和电连接到正常图案并与异常图案电隔离的导线（130）。 正常图案具有电连接到导电线的第一图案（112）和布置在第一图案之间的第二图案（114）。 第二图案连接到地面（150）。

Patent Agency Ranking