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公开(公告)号：KR1020150018326A
公开(公告)日：2015-02-23
申请号：KR1020130111880
申请日：2013-09-17
Applicant: 삼성전자주식회사
IPC: H01L27/11 , H01L21/8244
CPC classification number: H01L27/1104 , H01L21/823412 , H01L21/823807 , H01L27/0207 , H01L29/78
Abstract: 본 발명은 반도체 장치 및 그 제조 방법을 제공한다. 이 장치는 풀다운 트랜지스터의 소오스 영역 쪽의 코 임플란트 농도를 다른 곳보다 높게 함으로써, 포스트 어닐링 공정시에 소오스 영역 쪽의 헤일로 영역의 P형 불순물이 채널쪽으로 과도하게 확산되는 것을 방지하는 역할을 할 수 있다. 이로 인해, 각 단위 메모리 셀들 간의 포화 문턱 전압의 산포를 낮출 수 있다.
Abstract translation: 本发明提供一种半导体器件及其制造方法。 该装置通过增加下拉晶体管的源极侧的共注入浓度来防止源极区侧的卤素区的P型杂质在后退火工艺中过度扩散到沟道侧 与另一边。 由此，减小了单位存储单元之间的饱和阈值电压的分布。
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3.发明授权
公开(公告)号：KR100823695B1
公开(公告)日：2008-04-21
申请号：KR1020070023809
申请日：2007-03-12
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: H01L22/34
Abstract: A test structure for inspecting an allowable process margin is provided to easily determine an allowable process margin of each unit process by comparing sub patterns in which a defect is generated. A plurality of grounded conductive lines(140) are grounded to a substrate(800), positioned on a substrate. A plurality of non-grounded conductive lines(120) are electrically isolated from the surface of the substrate, separated from the grounded conductive line by a first interval. A plurality of sub patterns check the allowable process margin of an integrated circuit fabricating process by using a voltage contrast between the grounded conductive line and the non-grounded conductive line. A measurement unit can measure the DC current flowing through the grounded conductive line and the non-grounded conductive line, electrically connected to the grounded conductive line and the non-grounded conductive line.
Abstract translation: 提供了用于检查允许的处理余量的测试结构，以通过比较产生缺陷的子图案来容易地确定每个单元处理的允许处理余量。 多个接地导线（140）接地到位于基板上的基板（800）。 多个非接地导线（120）与衬底的表面电隔离，与接地导线隔开第一间隔。 多个子图案通过使用接地导线和非接地导线之间的电压对比来检查集成电路制造工艺的允许工艺余量。 测量单元可以测量流过接地导线和非接地导线的直流电流，电连接到接地导线和非接地导线。
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公开(公告)号：KR100801075B1
公开(公告)日：2008-02-11
申请号：KR1020060008700
申请日：2006-01-27
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G06F17/5081 , G06F2217/12 , Y02P90/265
Abstract: 홀의 시스템적 결함율을 이용하는 반도체 집적 회로 장치의 수율 향상 방법이 제공된다. 반도체 집적 회로 장치의 수율 향상 방법은 홀과, 홀을 둘러싸는 라인에서, 마주보는 홀의 변과 라인의 변 사이의 거리에 대해서 복수의 실험값을 결정하고, 각 실험값을 대표하는 복수의 테스트 패턴을 웨이퍼 상에 형성하여, 복수의 테스트 패턴으로부터 홀의 실험값별 시스템적 결함율을 산출하고, 테스트 패턴의 홀의 변의 길이를 이용하여, 홀의 실험값별 시스템적 결함율을 홀의 길이당 실험값별 시스템적 결함율로 환산하고, 관심 레이아웃 내에서, 마주보는 홀의 변과 라인의 변 사이의 거리가 각 실험값에 해당하는 홀의 변의 길이를 실험값별로 산출하고, 홀의 길이당 실험값별 시스템적 결함율과, 관심 레이아웃 내에서 실험값별로 산출된 홀의 변의 길이를 이용하여, 홀의 시스템적 결함율을 산출하는 것을 포함한다.
수율, 결함율, 실험값, 홀, 라인, 실험값별 시스템적 결함율, 실험값별 랜덤 결함율-
公开(公告)号：KR1020070078469A
公开(公告)日：2007-08-01
申请号：KR1020060008700
申请日：2006-01-27
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G06F17/5081 , G06F2217/12 , Y02P90/265
Abstract: A method and a system for enhancing yield of semiconductor integrated circuit devices using systematic fault rate of a hole is provided to calculate the systematic fault rate using distances between sides of the hole and the opposite sides of a shape surrounding the hole. Plural experimental values each corresponding to a distance from a side of a hole to an opposing side of a shape surrounding the hole are determined(S10). Plural test patterns representing each of the experimental values on a wafer are formed, and experimental value-based systematic fault rates are calculated from the test patterns(S20). The experimental value-based systematic fault rates of the hole are converted into experimental value-based systematic fault rates per unit hole length using a length of the sides of the hole of each of the test patterns(S30). The length of the side of the hole for which a distance between the side of the hole and the opposing side of the shape corresponds to each of experimental values in a desired layout is calculated(S40). A systematic fault rate of the hole is calculated using the experimental value-based systematic fault rates per unit hole length and the length of the sides of the hole calculated for the each of experimental values in the desired layout(S50).
Abstract translation: 提供使用孔的系统故障率提高半导体集成电路器件的产量的方法和系统，以使用孔的侧面和围绕孔的形状的相对侧之间的距离来计算系统故障率。 确定各自对应于从孔的一侧到围绕孔的形状的相对侧的距离的多个实验值（S10）。 形成表示晶片上每个实验值的多个测试图案，并根据测试图案计算实验值系统故障率（S20）。 使用每个测试图案的孔的边长度，将孔的基于实验值的系统故障率转换为每单位孔长度的基于实验值的系统故障率（S30）。 计算出孔的侧面与形状的相对侧之间的距离对应于所需布局中的每个实验值的孔的侧面的长度（S40）。 使用每个单位孔长度的基于实验值的系统故障率和针对所需布局中的每个实验值计算的孔的边长度来计算孔的系统故障率（S50）。
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Patent Agency Ranking
公开(公告)号：KR1020140029961A
公开(公告)日：2014-03-11
申请号：KR1020120096620
申请日：2012-08-31
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336 , H01L21/8238
CPC classification number: H01L27/1104 , H01L21/823842 , H01L21/82385 , H01L27/1116
Abstract: Provided is a semiconductor device. The semiconductor device comprises a semiconductor substrate including first and second areas, a first high permittivity pattern formed on the first area, a second high permittivity pattern formed on the second area and having a thickness equal to that of the first high permittivity pattern, a first work function control layer pattern formed on the first high permittivity pattern and having a first thickness, a second work function control layer pattern formed on the first work function control layer pattern and having a second thickness, a third work function control layer pattern formed on the second work function control layer pattern, having a third thickness less than the first thickness and having the same material as the first work function control layer pattern, and a fourth work function control layer pattern formed on the third work function control layer pattern, having a fourth thickness less than the second thickness and having the same material as the second work function control layer pattern.
Abstract translation: 提供一种半导体器件。 半导体器件包括：第一和第二区域的半导体衬底;形成在第一区域上的第一高介电常数图案;形成在第二区域上的厚度等于第一高介电常数图案的第二高介电常数图案; 形成在第一高介电常数图案上并具有第一厚度的功函数控制层图案，形成在第一功函数控制层图案上并具有第二厚度的第二功函数控制层图案，形成在第一厚度上的第三功函数控制层图案 第二工作功能控制层图案，具有小于第一厚度的第三厚度并且具有与第一功函数控制层图案相同的材料，以及形成在第三工作功能控制层图案上的第四工作功能控制层图案，其具有 第四厚度小于第二厚度并且具有与第二功函数相同的材料 控制层图案。
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7.发明授权반도체 집적 회로 장치의 레이아웃 분석 방법, 레이아웃 분석 시스템, 스탠다드 셀 라이브러리, 마스크 및 반도체 집적 회로 장치 有权半导体集成电路器件的布局分析方法，布局分析系统，标准单元库，掩模和半导体集成电路器件
公开(公告)号：KR100703982B1
公开(公告)日：2007-04-09
申请号：KR1020060006959
申请日：2006-01-23
Applicant: 삼성전자주식회사
IPC: H01L21/66
Abstract: 반도체 집적 회로 장치의 레이아웃 분석 방법, 레이아웃 분석 시스템, 스탠다드 셀 라이브러리, 마스크 및 반도체 집적 회로 장치가 제공된다. 반도체 집적 회로 장치의 레이아웃 분석 방법은 복수의 관심 레이아웃 각각의 랜덤 결함율, 시스템적 결함율, 파라미터적 결함율 및 면적을 산출하고, 복수의 랜덤 결함율, 시스템적 결함율, 파라미터적 결함율 및 면적을 이용하여, 복수의 관심 레이아웃의 면적별 결함율을 산출하고, 복수의 관심 레이아웃의 면적별 결함율을 이용하여, 복수의 관심 레이아웃 중 수정할 관심 레이아웃을 선정하는 것을 포함한다.
랜덤 결함율, 시스템적 결함율, 파라미터적 결함율Abstract translation: 提供了一种半导体集成电路器件的布局分析方法，布局分析系统，标准单元库，掩模和半导体集成电路器件。 该装置的半导体集成电路的布局分析方法各自的随机缺陷率多个感兴趣布局，全身性不良率，参产生的缺陷率和区域;以及多个随机缺陷率，全身性不良率，速率参数故障和 使用该区域计算多个感兴趣布局的区域缺陷率，并且使用多个感兴趣布局的区域缺陷率来从多个感兴趣布局中选择要校正的感兴趣布局。
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公开(公告)号：KR1020140029957A
公开(公告)日：2014-03-11
申请号：KR1020120096613
申请日：2012-08-31
Applicant: 삼성전자주식회사
IPC: H01L27/11 , H01L21/8244
CPC classification number: H01L27/1104
Abstract: A semiconductor device is provided. The semiconductor device includes at least one SRAM cell. Each SRAM cell includes a pull up transistor, a pull down transistor, and a pass gate transistor. The Tinv of the gate stack of the pass gate transistor is different from the Tinv of the gate stacks of the pull up transistor and the pull down transistor.
Abstract translation: 提供半导体器件。 半导体器件包括至少一个SRAM单元。 每个SRAM单元包括一个上拉晶体管，一个下拉晶体管和一个栅极晶体管。 栅极晶体管的栅极叠层的Tinv与上拉晶体管和下拉晶体管的栅极叠层的Tinv不同。
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公开(公告)号：KR100828026B1
公开(公告)日：2008-05-08
申请号：KR1020070033636
申请日：2007-04-05
Applicant: 삼성전자주식회사
IPC: H01L21/02 , H01L21/027
CPC classification number: G03F1/72 , H01L27/0207 , G03F7/70625 , G06F17/5068
Abstract: A method for correcting a layout of an integrated circuit design pattern and an apparatus for performing the same are provided to automatically correct the overall layout of a design pattern according to a certain criteria by using a combined defect characteristic function. A defect examination sample is selected from a substrate on which a plurality of processed patterns corresponding to design patterns are formed(S100). The processed patterns are classified according to a failure kind and stored per a failure unit in which a model pattern having a constant layout is designated(S200). The processed patterns stored per the failure unit are analyzed to create a plurality of defect characteristic functions which provides information regarding the generation degree of plural independent defects causing the failure(S300). A normalization coefficient is determined(S400). The normalization coefficient indicates the correlation between the defect characteristic functions. A single combined characteristic function is created based on the defect characteristic functions and the normalization coefficient(S500). The single combined characteristic function provides information regarding the generation degree of combined defects by taking into account the independent defects. The design pattern corresponding to the model pattern is evaluated on the basis of the single combined characteristic function and then corrected so as to minimize the generation degree of the combined defects(S600).
Abstract translation: 提供了一种用于校正集成电路设计图案的布局的方法和用于执行集成电路设计图案的装置的方法，以通过使用组合的缺陷特征函数来根据特定标准自动校正设计图案的总体布局。 从其上形成有对应于设计图案的多个处理图案的基板选择缺陷检查样本（S100）。 处理后的图案根据故障种类进行分类，并根据其中指定具有恒定布局的模型图案的故障单元进行存储（S200）。 对每个故障单元存储的处理图案进行分析，以创建多个缺陷特征函数，该功能提供关于引起故障的多个独立缺陷的生成程度的信息（S300）。 确定归一化系数（S400）。 归一化系数表示缺陷特征函数之间的相关性。 基于缺陷特征函数和归一化系数创建单一组合特征函数（S500）。 单一组合特征功能通过考虑独立缺陷提供有关组合缺陷生成度的信息。 基于单一组合特征函数对模型图案对应的设计模式进行评估，然后进行校正，以使组合缺陷的产生程度最小化（S600）。
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公开(公告)号：KR100755665B1
公开(公告)日：2007-09-05
申请号：KR1020050112549
申请日：2005-11-23
Applicant: 삼성전자주식회사
IPC: H01L21/02
CPC classification number: G06F17/504 , G06F17/5068
Abstract: A method and a system for improving yield of a semiconductor integrated circuit device are provided to design a yield-maximized layout by using a fault rate of a calculated design rule to correct a layout of interest. A plurality of experimental design rule values with respect to a design rule are determined(S20). A fault rate of each experimental design rule value is measured(S30). The number of features corresponding to the respective experimental design rule values are counted within a layout of interest(S40). A fault rate of the design rule is provided by using the fault rate of the experimental design rule and the number of features(S50). The layout of interest is corrected by using the fault rate of the design rule(S70). The design rule out of the plurality of design rules is a critical factor with respect to yield.
Abstract translation: 提供了一种用于提高半导体集成电路器件的产量的方法和系统，以通过使用计算的设计规则的故障率来校正感兴趣的布局来设计产量最大化的布局。 确定关于设计规则的多个实验设计规则值（S20）。 测量每个实验设计规则值的故障率（S30）。 对应于各实验设计规则值的特征的数量在感兴趣的布局内进行计数（S40）。 通过使用实验设计规则的故障率和特征数量来提供设计规则的故障率（S50）。 利用设计规则的故障率来校正感兴趣的布局（S70）。 多个设计规则中的设计规则是产量方面的关键因素。
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