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公开(公告)号：KR1020140029961A
公开(公告)日：2014-03-11
申请号：KR1020120096620
申请日：2012-08-31
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336 , H01L21/8238
CPC classification number: H01L27/1104 , H01L21/823842 , H01L21/82385 , H01L27/1116
Abstract: Provided is a semiconductor device. The semiconductor device comprises a semiconductor substrate including first and second areas, a first high permittivity pattern formed on the first area, a second high permittivity pattern formed on the second area and having a thickness equal to that of the first high permittivity pattern, a first work function control layer pattern formed on the first high permittivity pattern and having a first thickness, a second work function control layer pattern formed on the first work function control layer pattern and having a second thickness, a third work function control layer pattern formed on the second work function control layer pattern, having a third thickness less than the first thickness and having the same material as the first work function control layer pattern, and a fourth work function control layer pattern formed on the third work function control layer pattern, having a fourth thickness less than the second thickness and having the same material as the second work function control layer pattern.
Abstract translation: 提供一种半导体器件。 半导体器件包括：第一和第二区域的半导体衬底;形成在第一区域上的第一高介电常数图案;形成在第二区域上的厚度等于第一高介电常数图案的第二高介电常数图案; 形成在第一高介电常数图案上并具有第一厚度的功函数控制层图案，形成在第一功函数控制层图案上并具有第二厚度的第二功函数控制层图案，形成在第一厚度上的第三功函数控制层图案 第二工作功能控制层图案，具有小于第一厚度的第三厚度并且具有与第一功函数控制层图案相同的材料，以及形成在第三工作功能控制层图案上的第四工作功能控制层图案，其具有 第四厚度小于第二厚度并且具有与第二功函数相同的材料 控制层图案。
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公开(公告)号：KR100663360B1
公开(公告)日：2007-01-02
申请号：KR1020050032897
申请日：2005-04-20
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L27/0688 , H01L23/485 , H01L29/78 , H01L2924/0002 , H01L2924/00
Abstract: 박막 트랜지스터를 갖는 반도체 소자들 및 그 제조방법들이 제공된다. 상기 반도체 소자들은 반도체기판 및 상기 반도체기판 상에 제공된 하부 층간절연막이 구비된다. 상기 하부 층간절연막의 상부 또는 내부에 하부 반도체 바디가 배치된다. 상기 하부 반도체 바디 내에 형성된 하부 소오스 영역 및 하부 드레인 영역과 아울러서 상기 하부 소오스/드레인 영역들 사이의 상기 하부 반도체 바디의 적어도 2면을, 적어도 일부 감싸면서 가로지르는 하부 게이트 전극을 구비하는 하부 박막 트랜지스터가 배치된다.
하부 박막 트랜지스터, 하부 게이트 전극, 하부 반도체 바디, 플로팅 도전막 패턴-
公开(公告)号：KR1020060110558A
公开(公告)日：2006-10-25
申请号：KR1020050032897
申请日：2005-04-20
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L27/0688 , H01L23/485 , H01L29/78 , H01L2924/0002 , H01L27/088 , H01L2924/00
Abstract: A semiconductor device and a manufacturing method thereof are provided to restrain a narrow width effect due to the decrease of a channel width by using an improved thin film transistor structure. A semiconductor device comprises a semiconductor substrate(100), a lower interlayer dielectric on the substrate, a lower semiconductor body and a lower thin film transistor. The lower semiconductor body(125) is formed on or in the lower interlayer dielectric. The lower thin film transistor is composed of lower source and drain regions and a lower gate electrode. The lower source and the drain regions are formed within the lower semiconductor body. The lower gate electrode is formed between the lower source and the drain regions in order to enclose partially the lower semiconductor body.
Abstract translation: 提供半导体器件及其制造方法，以通过使用改进的薄膜晶体管结构来抑制由于沟道宽度的减小而导致的窄宽度效应。 半导体器件包括半导体衬底（100），衬底上的下层间电介质，下半导体本体和下薄膜晶体管。 下部半导体本体（125）形成在下部层间电介质中或其中。 下部薄膜晶体管由下部源极和漏极区域以及下部栅极电极构成。 下部源极和漏极区域形成在下部半导体本体内。 下栅电极形成在下源极和漏极区之间，以便部分地封装下半导体本体。
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公开(公告)号：KR101275758B1
公开(公告)日：2013-06-14
申请号：KR1020070072964
申请日：2007-07-20
Applicant: 삼성전자주식회사
IPC: H01L27/11
CPC classification number: H01L21/8221 , H01L27/0688 , H01L27/1108 , H01L27/1207
Abstract: 복수개의적층된트랜지스터들을구비하는반도체소자가제공된다. 상기반도체소자는반도체기판상에형성된하부절연막과, 상기하부절연막상에형성된상부채널바디패턴을구비한다. 상기상부채널바디패턴내에소오스영역및 드레인영역이제공되고, 상기소오스영역및 상기드레인영역사이의상기상부채널바디패턴상에비금속전송게이트전극이배치된다. 상기비금속전송게이트전극, 상기상부채널바디패턴및 상기하부절연막은중간절연막으로덮여지고, 상기중간절연막내에상기비금속전송게이트전극의적어도상부면과접촉하는금속워드라인이배치된다. 상기금속워드라인의측벽상에절연성스페이서가제공되고, 상기중간절연막및 상기하부절연막내에상기상부채널바디패턴내의상기소오스영역과접촉하는금속노드플러그가배치된다. 상기반도체소자의제조방법또한제공된다.
Abstract translation: 根据示例性实施例的半导体器件可以具有多个堆叠的晶体管。 半导体器件可以具有形成在半导体衬底上的下绝缘层和形成在下绝缘层上的上沟道体图案。 源极区域和漏极区域可以形成在上部通道主体图案内，并且非金属转移栅极电极可以设置在源极和漏极区域之间的上部通道主体图案上。 非金属转移栅电极，上通道体图案和下绝缘层可以被中间绝缘层覆盖。 金属字线可以设置在中间绝缘层内以接触非金属转移栅电极的至少上表面。 绝缘间隔物可以设置在金属字线的侧壁上。 金属节点插头可以设置在中间绝缘层和下绝缘层内以接触上通道主体图案的源区域。 示例性实施例还涉及制造上述半导体器件的方法。
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Patent Agency Ranking
公开(公告)号：KR1020090009566A
公开(公告)日：2009-01-23
申请号：KR1020070072964
申请日：2007-07-20
Applicant: 삼성전자주식회사
IPC: H01L27/11
CPC classification number: H01L21/8221 , H01L27/0688 , H01L27/1108 , H01L27/1207
Abstract: A semiconductor device having a plurality of laminated transistors and a manufacturing method thereof are provided to form a gate electrode of a thin film transistor functioning as a transmission transistor through a non-metal conductive material film, thereby reducing etching damage applied to a body pattern and improving an operation speed of the transmission transistor. A semiconductor device comprises a bottom insulating layer(23) formed on a semiconductor substrate(1), and an upper channel body pattern(27) formed on the bottom insulating layer. A source area(33s) and a drain area(33d) are provided within the upper channel body pattern. A non-metal transfer gate electrode(31a) is arranged on the upper channel body pattern between the drain area and the source area. The transfer gate electrode and the source/drain areas comprise a transmission transistor(TT1). The transmission transistor and the bottom insulating layer are covered with an intermediate insulating film(35). A metal word line(45) contacting at least an upper surface of the non-metal transfer gate electrode is arranged within the intermediate insulating film. An insulating spacer(43) is provided on a side wall of the metal word line A metal node plug(37) contacting the source area within the upper channel body pattern is arranged within the intermediate insulating film and bottom insulating layer.
Abstract translation: 提供具有多个层叠晶体管的半导体器件及其制造方法，以通过非金属导电材料膜形成用作透射晶体管的薄膜晶体管的栅电极，从而减少施加于主体图案的蚀刻损伤， 提高了传输晶体管的操作速度。 半导体器件包括形成在半导体衬底（1）上的底部绝缘层（23）和形成在底部绝缘层上的上部通道体图案（27）。 源区域（33s）和漏区（33d）设置在上通道体图案内。 在漏极区域和源极区域之间的上通道主体图案上设置有非金属转移栅电极（31a）。 传输栅极电极和源极/漏极区域包括透射晶体管（TT1）。 透射晶体管和底部绝缘层被中间绝缘膜（35）覆盖。 与非金属转移栅电极的至少上表面接触的金属字线（45）布置在中间绝缘膜内。 在金属字线A的侧壁上设置绝缘间隔物（43），在中间绝缘膜和底部绝缘层内配置有与上部通道主体图形内的源极区域接触的金属节点插头（37）。
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公开(公告)号：KR1020100003629A
公开(公告)日：2010-01-11
申请号：KR1020080063617
申请日：2008-07-01
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L27/0688 , H01L21/8221 , H01L21/823475
Abstract: PURPOSE: A semiconductor memory device including stack transistors and a method for manufacturing the same are provided to reduce a layout area of a peripheral circuit region by stacking the transistors of the peripheral circuit region. CONSTITUTION: A semiconductor substrate(SUB) has a cell region(C) and a peripheral circuit region(P). First transistors are formed on the semiconductor substrate. The first semiconductor layer is provided on the first transistor and is combined with a bonding method. Second transistors provided on the first semiconductor layer are included. The first and second transistors are provided to the peripheral circuit regions of the first semiconductor layer and the semiconductor substrate. A metal layer(7e) is formed on the gates of the first and second transistors provided to the peripheral circuit regions of the first semiconductor layer and the semiconductor substrate.
Abstract translation: 目的：提供包括堆叠晶体管的半导体存储器件及其制造方法，以通过堆叠外围电路区域的晶体管来减少外围电路区域的布局面积。 构成：半导体衬底（SUB）具有单元区域（C）和外围电路区域（P）。 第一晶体管形成在半导体衬底上。 第一半导体层设置在第一晶体管上，并与结合方法组合。 包括设置在第一半导体层上的第二晶体管。 第一和第二晶体管被提供给第一半导体层和半导体衬底的外围电路区域。 在设置在第一半导体层和半导体衬底的外围电路区域的第一和第二晶体管的栅极上形成金属层（7e）。
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公开(公告)号：KR1020140029957A
公开(公告)日：2014-03-11
申请号：KR1020120096613
申请日：2012-08-31
Applicant: 삼성전자주식회사
IPC: H01L27/11 , H01L21/8244
CPC classification number: H01L27/1104
Abstract: A semiconductor device is provided. The semiconductor device includes at least one SRAM cell. Each SRAM cell includes a pull up transistor, a pull down transistor, and a pass gate transistor. The Tinv of the gate stack of the pass gate transistor is different from the Tinv of the gate stacks of the pull up transistor and the pull down transistor.
Abstract translation: 提供半导体器件。 半导体器件包括至少一个SRAM单元。 每个SRAM单元包括一个上拉晶体管，一个下拉晶体管和一个栅极晶体管。 栅极晶体管的栅极叠层的Tinv与上拉晶体管和下拉晶体管的栅极叠层的Tinv不同。
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公开(公告)号：KR101923946B1
公开(公告)日：2018-11-30
申请号：KR1020120096620
申请日：2012-08-31
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336 , H01L21/8238
CPC classification number: H01L27/1104 , H01L21/823842 , H01L21/82385 , H01L27/1116
Abstract: 반도체장치가제공된다. 반도체장치는, 제1 및제2 영역을포함하는반도체기판, 제1 영역상에형성된제1 고유전율막패턴, 제2 영역상에형성되고상기제1 고유전율막패턴과동일한두께를갖는제2 고유전율막패턴, 제1 고유전율막패턴상에형성되고제1 두께를갖는제1 일함수조절막패턴, 제1 일함수조절막패턴상에형성되고제2 두께를갖는제2 일함수조절막패턴, 제2 고유전율막패턴상에형성되고제1 두께보다작은제3 두께를가지며, 제1 일함수조절막패턴과동일한물질로이루어진제3 일함수조절막패턴, 및제3 일함수조절막패턴상에형성되고제2 두께보다큰 제4 두께를가지며, 제2 일함수조절막패턴과동일한물질로이루어진제4 일함수조절막패턴을포함한다.
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