公开(公告)号：KR100526344B1

公开(公告)日：2005-11-08

申请号：KR1020030055744

申请日：2003-08-12

Applicant: 삼성전자주식회사

Inventor： 신순균

IPC: H03K17/00

CPC classification number: H02M3/073 ,  H02M2001/0045 ,  H03K17/063

Abstract: 안정적인 승압 전압을 발생하기 위한 승압 전압 제어장치 및 방법이 개시된다. 본 발명의 전압 발생부는 입력전압을 소정 레벨로 승압시킨 승압전압을 발생하고, 전압 제어부는 기준전압과 승압전압의 차전압에 따른 제어전류를 발생하고, 제어전류에 따라 승압전압의 레벨을 제어한다. 따라서, 승압전압을 제어전류에 따라 제어하므로, 리플전압을 감소시킬 수 있다.

公开(公告)号：KR1020040051420A

公开(公告)日：2004-06-18

申请号：KR1020020079348

申请日：2002-12-12

Applicant: 삼성전자주식회사

Inventor： 신순균

IPC: G11C7/10

CPC classification number: H03K19/00315

Abstract: PURPOSE: An input buffer is provided to prevent the leakage current by pulling-up a level of a pad to a power supply voltage level in case that the pad is a floating state. CONSTITUTION: A high voltage detection circuit(100) generates a high voltage detection signal(VDET) when a floating well voltage(VFW) is applied and a voltage greater than power supply voltage level(VDD) is applied to a pad(20). The high voltage detection circuit(100) resets the high voltage detection signal(VDET) in response to a high voltage reset signal(VRE). A control voltage and floating well voltage generation circuit(110) generates the floating well voltage(VFW) and a control voltage(CON) when high voltage is applied to the pad(20). The control voltage and floating well voltage generation circuit(110) generates the power supply voltage(VDD) by the floating well voltage(VFW) and generates a ground voltage by the control voltage(CON) when voltage lower than the high voltage is applied to the pad(20). A PMOS(P-channel Metal Oxide Semiconductor) transistor(P2) is turned off when the floating well voltage(VFW) and the control voltage(CON) becomes the voltage applied to the pad(20), and is turned on when the floating well voltage(VFW) becomes a power voltage(VDD) and the control voltage(CON) becomes the ground voltage, thereby pulling-up the pad(20) to the level of the power voltage(VDD). An NMOS(N-channel Metal Oxide Semiconductor) transistor(N2) transmits the voltage applied to the pad(20). A buffer(BUF2) transits a level of an input signal when a level of a signal transmitted through the NMOS transistor(N2) reaches to a trip voltage thereof.

Abstract translation: 目的：提供一个输入缓冲器，用于在垫为浮动状态的情况下，通过将焊盘电平提升到电源电压电平来防止漏电流。 构成：当施加浮动井电压（VFW）并且将大于电源电压电平（VDD）的电压施加到焊盘（20）时，高压检测电路（100）产生高电压检测信号（VDET）。 高压检测电路（100）响应于高电压复位信号（VRE）而复位高电压检测信号（VDET）。 当对电极垫（20）施加高电压时，控制电压和浮动井电压产生电路（110）产生浮动井电压（VFW）和控制电压（CON）。 控制电压和浮动井电压产生电路（110）通过浮动井电压（VFW）产生电源电压（VDD），并且当低于施加高电压的电压时通过控制电压（CON）产生接地电压 垫（20）。 当浮动阱电压（VFW）和控制电压（CON）变为施加到焊盘（20）的电压时，PMOS（P沟道金属氧化物半导体）晶体管（P2）截止，并且当浮置 阱电压（VFW）变为电源电压（VDD），控制电压（CON）成为接地电压，从而将焊盘（20）上拉至电源电压（VDD）的水平。 NMOS（N沟道金属氧化物半导体）晶体管（N2）传输施加到焊盘（20）的电压。 当通过NMOS晶体管（N2）传输的信号的电平达到其跳闸电压时，缓冲器（BUF2）转换输入信号的电平。

公开(公告)号：KR100429870B1

公开(公告)日：2004-05-03

申请号：KR1020010007274

申请日：2001-02-14

Applicant: 삼성전자주식회사

Inventor： 신순균

IPC: G11C11/40

CPC classification number: H03K19/00384

Abstract: An output buffer for buffering output data includes a bias voltage generator for generating first and second bias voltages responsive to a reference voltage, an output driver in signal communication with the bias voltage generator for driving an output terminal, a first slew rate controller in signal communication with the output driver for controlling a pull-up slew rate of the output driver in response to the output data and the first bias voltage, a second slew rate controller in signal communication with the output driver for controlling a pull-down slew rate of the output driver in response to the output data and the second bias voltage, and a slew rate compensator in signal communication with the output ends of the first and second slew rate controllers and the output terminal for compensating for slew rate variation in response to a change in the load capacitance of the output terminal.

Abstract translation: 用于缓冲输出数据的输出缓冲器包括用于产生响应于参考电压的第一和第二偏置电压的偏置电压发生器，与偏置电压发生器信号通信以用于驱动输出端子的输出驱动器，信号通信中的第一转换速率控制器 用于响应于所述输出数据和所述第一偏置电压来控制所述输出驱动器的上拉转换速率的输出驱动器;与所述输出驱动器进行信号通信以控制所述输出驱动器的下拉转换速率的第二转换速率控制器， 输出驱动器，响应于输出数据和第二偏置电压;以及转换速率补偿器，与第一和第二转换速率控制器的输出端信号通信，并且输出端用于响应于第一和第二转换速率控制器的变化而补偿转换速率变化 输出端子的负载电容。

公开(公告)号：KR1020000010306A

公开(公告)日：2000-02-15

申请号：KR1019980031177

申请日：1998-07-31

Applicant: 삼성전자주식회사

Inventor： 신순균 ,  함석헌 ,  권규형

IPC: H01L21/301

Abstract: PURPOSE: A semiconductor device having a chip size reduced by decreasing a mechanical stress applied in bonding is disclosed. CONSTITUTION: A N-1th metal layer consisting of a plurality of patterns is formed on a semiconductor substrate(50) with an insulating layer formed thereon. A N-1th interlayer insulating layer is formed on the N-1th metal layer. A Nth metal layer having concave-convex surface at a part on which bonding pad is to be formed is formed on the N-1th interlayer insulating layer. Finally, a passivation layer(66) constituting the bonding pad by partially exposing the Nth metal layer is formed on the Nth metal layer. Also, the Nth metal layer is electrically connected to the N-1th metal layer through a plurality of via-holes passing through the interlayer insulating layer. Thereby, it is possible to provide the semiconductor device having the chip size reduced by decreasing the mechanical stress applied in bonding although an interval between the bonding pad and the patterns formed around thereof is decreased.

Abstract translation: 目的：公开了通过降低在接合中施加的机械应力来减小芯片尺寸的半导体器件。 构成：在其上形成有绝缘层的半导体衬底（50）上形成由多个图案组成的N-1金属层。 在第N-1层金属层上形成N-1层间绝缘层。 在N-1层间绝缘层上形成第N个金属层，其在要形成接合焊盘的部分上具有凹凸表面。 最后，在第N金属层上形成通过部分曝光第N金属层构成接合焊盘的钝化层（66）。 此外，第N金属层通过穿过层间绝缘层的多个通孔与第N-1金属层电连接。 由此，尽管接合焊盘和形成在其周围的图案之间的间隔减小，但可以通过减小接合中施加的机械应力来提供具有减小的芯片尺寸的半导体器件。

公开(公告)号：KR100871810B1

公开(公告)日：2008-12-03

申请号：KR1020070028353

申请日：2007-03-23

Applicant: 삼성전자주식회사

Inventor： 이충훈 ,  신순균

IPC: G06F7/58

CPC classification number: G06F7/588 ,  H04L9/0861

Abstract: 랜덤 신호 발생기 및 이를 포함하는 난수 발생기가 개시된다. 랜덤 신호 발생기에서, 잡음원은 불규칙한 잡음 신호를 발생한다. 차동 노이즈 발생 회로는 입력 단자쌍이 출력 단자쌍과 연결되어 셀프-바이어스되고 입력 단자쌍에 잡음 신호들이 각각 인가되어 출력 단자쌍을 통하여 차동 노이즈 신호를 발생한다. 증폭 회로는 차동 노이즈 신호를 증폭하여 차동 증폭 신호를 출력하고 싱글-엔드 증폭기는 차동 증폭 신호에 기초하여 천이 시점이 불규칙한 랜덤 신호를 출력한다. 차동 셀프-바이어스 구조에 의해 노이즈에 둔감하고랜덤성이 우수한 랜덤 신호 및 난수를 발생시킬 수 있다.
난수, 랜덤 신호, 셀프-바이어스, TRNG(True Random Number Generator)

公开(公告)号：KR1020080086567A

公开(公告)日：2008-09-26

申请号：KR1020070028353

申请日：2007-03-23

Applicant: 삼성전자주식회사

Inventor： 이충훈 ,  신순균

IPC: G06F7/58

CPC classification number: G06F7/588 ,  H04L9/0861

Abstract: A random signal generator, a random number generating including the random signal generator and a random number generating method are provided to generate a random signal and a random number insensitive to noise by adopting a differential self-bias structure. A random signal generator(100) includes a differential noise generating circuit(110), an amplification circuit(130) and a single-end amplifier(150). The differential noise generating circuit is self-biased and generates a differential noise signal. The amplification circuit amplifies the differential noise signal and outputs a differential amplification signal. The single-end amplifier outputs a random signal having irregular transition points based on the differential amplification signal.

Abstract translation: 提供随机信号发生器，包括随机信号发生器的随机数生成器和随机数生成方法，以通过采用差分自偏压结构来产生随机信号和对噪声不敏感的随机数。 随机信号发生器（100）包括差分噪声产生电路（110），放大电路（130）和单端放大器（150）。 差分噪声产生电路是自偏置的并产生差分噪声信号。 放大电路放大差分噪声信号并输出​​差分放大信号。 单端放大器基于差分放大信号输出具有不规则转变点的随机信号。

公开(公告)号：KR100829793B1

公开(公告)日：2008-05-16

申请号：KR1020060076570

申请日：2006-08-14

Applicant: 삼성전자주식회사

Inventor： 신순균

IPC: G06F7/58 ,  G06F7/00

CPC classification number: G06F7/588 ,  H03B29/00 ,  H03K3/84 ,  H03K5/135

Abstract: 랜덤 신호 발생기 및 이를 포함하는 난수 발생기가 개시된다. 랜덤 신호 발생기에서, 잡음원은 불규칙한 잡음 신호를 발생한다. 셀프-바이어스 인버터는 입력 단자가 출력 단자와 연결되어 셀프-바이어스되고, 입력 단자로 인가되는 잡음 신호를 감지하여 감지 잡음 신호를 출력 단자를 통하여 출력한다. 증폭 회로는 감지 잡음 신호를 증폭하여 논리 하이 레벨 및 논리 로우 레벨의 지속시간이 불규칙한 랜덤 신호를 출력한다. 따라서, 적은 소비 전력으로 랜덤성이 우수한 랜덤 신호 및 난수를 발생할 수 있다.
난수, 잡음원, 셀프-바이어스, 커플링 커패시터, random number, noise source

公开(公告)号：KR1020070015773A

公开(公告)日：2007-02-06

申请号：KR1020050070345

申请日：2005-08-01

Applicant: 삼성전자주식회사

Inventor： 신순균

IPC: H03K19/0175 ,  H03K19/00

CPC classification number: H03K17/166

Abstract: 슬루율 제어가 가능한 반도체 집적회로의 출력 구동회로가 개시되어 있다. 반도체 집적회로의 출력 구동회로는 프리 드라이버, 및 메인 드라이버를 구비한다. 프리 드라이버는 제 1 입력신호를 버퍼링하여 제 1 게이트 제어신호를 발생시켜 제 1 노드에 제공하고, 제 2 입력신호를 버퍼링하여 제 2 게이트 제어신호를 발생시켜 제 2 노드에 제공한다. 메인 드라이버는 제 1 게이트 제어신호 및 제 2 게이트 제어신호에 응답하여 출력신호를 발생시켜 출력노드에 제공한다. 출력신호가 상승 천이하는 동안 출력노드와 상기 제 1 노드 사이에 제 1 용량성 전류 경로가 형성되고, 출력신호가 하강 천이하는 동안 출력노드와 제 2 노드 사이에 제 2 용량성 전류 경로가 형성된다. 따라서, 출력 구동회로는 공정, 전압, 온도 등의 동작환경에 무관하게 일정한 슬루율을 가지는 출력신호를 발생시킬 수 있다.

Abstract translation: 公开了一种能够进行转换速率控制的半导体集成电路的输出驱动电路。 半导体集成电路的输出驱动器电路包括预驱动器和主驱动器。 预驱动器是第一产生第一栅极控制信号到缓冲器提供到第一节点的输入信号，并以缓冲所述第二输入信号，以产生提供给所述第二节点的第二栅极控制信号。 主驱动器响应于第一栅极控制信号和第二栅极控制信号而产生输出信号，并将输出信号提供给输出节点。 的输出信号与第一输出节点和所述上升转变期间所述第一节点之间的电容性电流路径形成的，下降转变的输出信号期间形成在输出节点和第二节点之间的第二电容性电流路径 。 因此，输出驱动电路可以产生具有恒定转换速率的输出信号，而与过程，电压，温度等的工作环境无关。

公开(公告)号：KR1020050018356A

公开(公告)日：2005-02-23

申请号：KR1020030055744

申请日：2003-08-12

Applicant: 삼성전자주식회사

Inventor： 신순균

IPC: H03K17/00

CPC classification number: H02M3/073 ,  H02M2001/0045 ,  H03K17/063

Abstract: PURPOSE: A boosting voltage control apparatus and a method thereof are provided to generate a stable voltage by reducing a ripple voltage. CONSTITUTION: A voltage generation part generates a boosting voltage by boosting an input voltage. A voltage control part generates a control current according to a difference voltage between a reference voltage and the boosting voltage, and controls the level of the boosting voltage according to the control current. According to the voltage generation part, a clock generation part(200) generates the first and the second and the third clock having an operation period not overlapped each other. A voltage level conversion part(210) converts the level of the input voltage by the first clock, and outputs a switch control signal according to the input voltage whose level is converted. The first and the second switch(S1,S2) operate according to the second and the third clock. The third and the fourth switch(S3,S4) operate according to the switch control signal. And a voltage charging capacitor(Cpump) charges corresponding to the input voltage while the first and the third switch are turned on, and outputs a voltage corresponding to the charged charges while the second and the fourth switch are turned off.

Abstract translation: 目的：提供升压电压控制装置及其方法，以通过减小纹波电压来产生稳定的电压。 构成：电压产生部通过提高输入电压来产生升压电压。 电压控制部根据参考电压和升压电压之间的差电压产生控制电流，并根据控制电流来控制升压电压的电平。 根据电压生成部，时钟生成部（200）生成第一和第二及第三时钟具有不重叠的运算周期。 电压电平转换部分（210）将输入电压的电平转换为第一时钟，并根据其电平被转换的输入电压输出开关控制信号。 第一和第二开关（S1，S2）根据第二和第三时钟进行工作。 第三和第四开关（S3，S4）根据开关控制信号进行工作。 并且当第一和第三开关导通时，电压充电电容器（Cpump）对应于输入电压充电，并且在第二和第四开关断开时输出与充电电荷相对应的电压。

公开(公告)号：KR1020020054893A

公开(公告)日：2002-07-08

申请号：KR1020000084158

申请日：2000-12-28

Applicant: 삼성전자주식회사

Inventor： 신순균

IPC: G11C7/10

Abstract: PURPOSE: An output driver for reducing a variation of a slewing rate of output data in a semiconductor device and a method for reducing a variation of slewing data are provided to reduce the variation of slewing rate of output data by improving a structure of an output driver circuit. CONSTITUTION: The supply voltage(VDD) is applied to a source of an output PMOS transistor. The first output data are applied to a gate of the output PMOS transistor. A source of compensating PMOS transistor is connected with a drain of the output PMOS transistor. The second compensating voltage is applied to a gate of the compensating PMOS transistor. A drain of the compensating PMOS transistor is connected with an output node(DN). A compensating NMOS transistor has a drain connected with the output node(DN) and a gate for receiving the second compensating voltage. The compensating PMOS transistor and the compensating NMOS transistor reduce the variation of slewing rates of the first output data(DATA1) and the second output data(DATA2). An output NMOS transistor has a drain connected with the source of the compensating NMOS transistor, a gate for receiving the second output data(DATA2), and a source connected with a ground.

Abstract translation: 目的：提供一种用于减少半导体器件中的输出数据的回转速度的变化的输出驱动器以及用于减小回转数据的变化的方法，以通过改善输出驱动器的结构来减小输出数据的转换速率的变化 电路。 构成：电源电压（VDD）被施加到输出PMOS晶体管的源极。 第一输出数据被施加到输出PMOS晶体管的栅极。 补偿PMOS晶体管的源极与输出PMOS晶体管的漏极连接。 第二补偿电压被施加到补偿PMOS晶体管的栅极。 补偿PMOS晶体管的漏极与输出节点（DN）连接。 补偿NMOS晶体管具有与输出节点（DN）连接的漏极和用于接收第二补偿电压的栅极。 补偿PMOS晶体管和补偿NMOS晶体管减小第一输出数据（DATA1）和第二输出数据（DATA2）的转换速率的变化。 输出NMOS晶体管具有与补偿NMOS晶体管的源极连接的漏极，用于接收第二输出数据（DATA2）的栅极和与地连接的源极。