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公开(公告)号：KR1020100010743A
公开(公告)日：2010-02-02
申请号：KR1020080071755
申请日：2008-07-23
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/144 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1683 , H01L45/143 , H01L45/1691
Abstract: PURPOSE: An electric device and a method of forming the same are provided to prevent the program state of the fuse phase change device from being changed in high mounting process by keeping different thermal characteristics of a fuse and cell of phase change device. CONSTITUTION: A substrate(100) comprises a cell region(A) and fuse regions(B). Signal wires(112c,112f) are formed on the substrate. The first phase change pattern(130f) is formed on the signal wire. The second phase change pattern(130c) is formed in the first phase change pattern. Top wirings(160c,160f) are formed in the phase change pattern. The crystallization temperature of the first phase change pattern is higher than that of the second phase change pattern. The bottom electrode is interposed between the signal wire and the first phase change pattern.
Abstract translation: 目的：提供电气装置及其形成方法，以通过保持相变装置的熔断器和电池的不同的热特性来防止熔断器相变装置的编程状态在高安装过程中发生变化。 构成：衬底（100）包括电池区（A）和熔丝区（B）。 信号线（112c，112f）形成在基板上。 第一相变图案（130f）形成在信号线上。 第二相变图案（130c）以第一相变图案形成。 顶部布线（160c，160f）形成为相变图案。 第一相变图案的结晶温度高于第二相变图案的结晶温度。 底部电极介于信号线和第一相变图案之间。
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公开(公告)号：KR1020090097362A
公开(公告)日：2009-09-16
申请号：KR1020080022448
申请日：2008-03-11
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/1675 , G11C11/5664 , G11C11/5678 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683 , H01L45/04
Abstract: A resistance memory element and a method for forming the same are provided to reduce thermal interference between adjacent phase change memory elements by forming an insulating film with low thermal conductivity surrounding the phase change memory element. A resistance memory element is formed on a substrate(100). A first insulating layer(150) covers the side of the resistive memory element. A wiring is formed on the resistance memory element. A second insulating layer(160) covers the side of the wiring. The intensity of the first insulating layer is higher than the intensity of the second insulating layer. The dielectric constant of the second insulating layer is lower than the dielectric constant of the first insulating layer.
Abstract translation: 提供了一种电阻存储元件及其形成方法，用于通过围绕相变存储元件形成具有低热导率的绝缘膜来减少相邻相变存储元件之间的热干扰。 电阻存储元件形成在衬底（100）上。 第一绝缘层（150）覆盖电阻式存储元件的一侧。 在电阻存储元件上形成布线。 第二绝缘层（160）覆盖布线的一侧。 第一绝缘层的强度高于第二绝缘层的强度。 第二绝缘层的介电常数低于第一绝缘层的介电常数。
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公开(公告)号：KR100626388B1
公开(公告)日：2006-09-20
申请号：KR1020040083690
申请日：2004-10-19
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , G11C11/15 , H01L27/115 , H01L21/28
CPC classification number: H01L45/06 , H01L27/2436 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666
Abstract: 저항 산포 불량이 발생하지 않으면서 프로그램 전류를 효과적으로 낮출 수 있는 상변환 기억 소자 및 그 형성 방법을 개시한다. 이 상변환 기억 소자는 층간절연막 상의 하부전극 패턴; 상기 하부전극 패턴 상에 위치하는 절연막 패턴; 상기 절연막 패턴과 상기 하부전극 패턴을 관통하여 상기 하부전극 패턴 및 상기 층간절연막과 접하는 상변환 패턴; 및 상기 상변환 패턴 상의 상부전극을 구비한다.
상변환 기억 소자-
公开(公告)号：KR100583967B1
公开(公告)日：2006-05-26
申请号：KR1020040051730
申请日：2004-07-02
Applicant: 삼성전자주식회사
IPC: H01L21/8247
Abstract: 이중 캐핑막을 갖는 상변화 기억소자 및 그 제조방법을 제공한다. 상기 상변화 기억소자는 반도체기판 상에 층간절연막을 구비한다. 상기 층간절연막을 관통하는 하부전극이 배치된다. 상기 층간절연막 상에 배치되되, 상기 하부전극과 전기적으로 접속된 상변화 저항체(phase change resistor)가 배치된다. 상기 상변화 저항체(phase change resistor) 측벽들을 덮는 GST, Sb-Te 또는 Ge-Te 계열의 합금막으로 구성된 제 1 캐핑막 스페이서가 배치된다. 상기 제 1 캐핑막 스페이서를 갖는 반도체기판 상에 제 2 캐핑막이 배치된다.
상변화 저항체, 상변화 물질막, 제 1 캐핑막 스페이서, 제 2 캐핑막-
公开(公告)号：KR1020060034530A
公开(公告)日：2006-04-24
申请号：KR1020040083690
申请日：2004-10-19
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , G11C11/15 , H01L27/115 , H01L21/28
CPC classification number: H01L45/06 , H01L27/2436 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666
Abstract: 저항 산포 불량이 발생하지 않으면서 프로그램 전류를 효과적으로 낮출 수 있는 상변환 기억 소자 및 그 형성 방법을 개시한다. 이 상변환 기억 소자는 층간절연막 상의 하부전극 패턴; 상기 하부전극 패턴 상에 위치하는 절연막 패턴; 상기 절연막 패턴과 상기 하부전극 패턴을 관통하여 상기 하부전극 패턴 및 상기 층간절연막과 접하는 상변환 패턴; 및 상기 상변환 패턴 상의 상부전극을 구비한다.
상변환 기억 소자-
Patent Agency Ranking
公开(公告)号：KR1020110081623A
公开(公告)日：2011-07-14
申请号：KR1020100001878
申请日：2010-01-08
Applicant: 삼성전자주식회사 , 서울대학교산학협력단
CPC classification number: G11C13/0002 , G11C13/0023 , G11C2213/71 , H01L27/101 , H01L27/102 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146
Abstract: PURPOSE: A semiconductor devices and a method of driving the same are provided to implement high integration by preventing the interference between nonvolatile memory cells. CONSTITUTION: In a semiconductor devices and a method of driving the same, a unit cell structure(1) comprises electrode layers(M1,M2), a bipolar resistance memory material film(RM1), and a unipolar resistance memory material film(RM2) The bipolar resistance memory material film and the unipolar resistance memory material film are formed between electrode layers which are opposite to each other. The bipolar resistance memory material film and the unipolar resistance memory material film are electrically serially connected. The electrode layers include resistance memory material films which are connected to conductive lines respectively.
Abstract translation: 目的：提供半导体器件及其驱动方法，以通过防止非易失性存储单元之间的干扰来实现高集成度。 构成：在半导体器件及其驱动方法中，单元电池结构（1）包括电极层（M1，M2），双极性电阻记忆材料膜（RM1）和单极电阻存储材料膜（RM2） 双极性电阻记忆材料膜和单极电阻记忆材料膜形成在彼此相对的电极层之间。 双极性电阻记忆材料膜和单极性电阻记忆材料膜电连接。 电极层包括分别连接到导线的电阻记忆材料膜。
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17.发明公开상변화 메모리 유닛의 형성 방법, 이를 이용한 상변화메모리 장치의 제조 방법 및 이에 따라 형성된 상변화메모리 장치 无效形成相变存储器单元的方法，使用该相变存储单元制造相变存储器件的方法，以及使用其制造的相变存储器件
公开(公告)号：KR1020090108479A
公开(公告)日：2009-10-15
申请号：KR1020080033916
申请日：2008-04-11
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/144 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1675 , H01L21/67063 , H01L21/76256 , H01L45/143 , H01L45/1691
Abstract: PURPOSE: A method for forming a phase change memory unit, a manufacturing method of a phase change memory device using the same, and a phase change memory device formed by the same are provided to prevent deterioration of a phase change material film. CONSTITUTION: A conductive film is formed on a substrate(100) in which a trench is formed. A first electrode is formed by flattening a top part of the conductive film until a top surface of the substrate is exposed. A second spacer is formed, and covers a part of the first electrode. A phase change material film is formed on the first electrode and the second spacer. A second electrode is formed on the phase change material film.
Abstract translation: 目的：提供一种用于形成相变存储器单元的方法，使用该相变存储器单元的相变存储器件的制造方法以及由其形成的相变存储器件，以防止相变材料膜的劣化。 构成：在形成有沟槽的基板（100）上形成导电膜。 第一电极通过使导电膜的顶部平坦化直到基板的顶表面露出而形成。 形成第二间隔物，并覆盖第一电极的一部分。 相变材料膜形成在第一电极和第二间隔物上。 在相变材料膜上形成第二电极。
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公开(公告)号：KR1020090003881A
公开(公告)日：2009-01-12
申请号：KR1020070067620
申请日：2007-07-05
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144
Abstract: The method of manufacturing the multi-bit memory device and the device is provided to form the different kind phase changeable layer for the multi-bit memory device by diffusing the heteroelement to the phase changeable layer. The phase changeable layer(173) is formed on the substrate. The glue layer(181) having heteroelement is formed on the phase changeable layer. The heteroelement is diffused within the phase changeable layer. The different kind phase changeable layer(177') is formed. The phase changeable layer is formed by using two or more compounds selected in the group consisting of the Ge, Sb, Te, Se, Bi, Pb, Sn, Ag, Au, As, Pd, In, Ti, S, Si, P, O and C.
Abstract translation: 提供制造多位存储器件和器件的方法，通过将异质元件扩散到相变层来形成用于多位存储器件的不同种类的相变层。 相变层（173）形成在基板上。 具有异质元素的胶层（181）形成在相变层上。 异相元件在相变层内扩散。 形成不同种类的相变层（177'）。 相变层通过使用选自Ge，Sb，Te，Se，Bi，Pb，Sn，Ag，Au，As，Pd，In，Ti，S，Si，P中的两种以上的化合物形成 ，O和C.
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公开(公告)号：KR1020090000489A
公开(公告)日：2009-01-07
申请号：KR1020070064589
申请日：2007-06-28
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L45/06 , H01L27/2409
Abstract: A phase change memory device and a manufacturing method thereof are provided to reduce a contact area between a phase change pattern and a diode with simple processes by directly contacting the diode to the phase change pattern without a bottom electrode. An element isolation region limiting a plurality of active areas is arranged in a semiconductor substrate. A plurality of doping lines(110) doped with impurities in the active area is extended to a first direction(WD). An wiring pattern(190) is extended to a second direction(BD) intersecting the first direction. Diodes(130) are formed in the spot where wiring patterns and doping lines are intersected. Phase change patterns(160) are interposed between the diodes and the wiring patterns. The phase change patterns are extended to the second direction under the wiring patterns. A spacer is equipped in the side wall of the phase change patterns in order to prevent the damage of the phase change patterns.
Abstract translation: 提供了一种相变存储器件及其制造方法，通过将二极管直接接触到没有底部电极的相变图案，通过简单的处理来减小相变图案和二极管之间的接触面积。 限制多个有源区域的元件隔离区域被布置在半导体衬底中。 在有源区域中掺杂有杂质的多个掺杂线（110）延伸到第一方向（WD）。 布线图案（190）延伸到与第一方向相交的第二方向（BD）。 二极管（130）形成在布线图案和掺杂线相交的位置。 相变图案（160）插在二极管和布线图案之间。 在布线图案下，相变图案延伸到第二方向。 为了防止相变图案的损坏，在相变图案的侧壁中配备有间隔件。
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公开(公告)号：KR100827661B1
公开(公告)日：2008-05-07
申请号：KR1020060106532
申请日：2006-10-31
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/144 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/1675 , G11C13/0004
Abstract: A phase change memory device and a manufacturing method thereof are provided to improve phase change efficiency, when a program current is applied on the phase change memory device, by insulating a first conductive pattern from a phase change material. A phase change memory device includes a semiconductor substrate(30), a phase change material pattern(56), a first conductive film pattern(52a), and a second conductive film pattern(52b). The phase change material pattern is provided on the substrate. The first conductive film pattern is arranged to be apart from the phase change material pattern. The second conductive film pattern is contacted with a sidewall of the first conductive film pattern and the phase change material pattern. A buffer pattern(58) is applied between the phase change material pattern and the first conductive film pattern. The buffer pattern is partially contacted with a sidewall of the second conductive film pattern.
Abstract translation: 提供了一种相变存储器件及其制造方法，通过使相位变化材料的第一导电图案绝缘，在相变存储器件上施加编程电流时，提高相变效率。 相变存储器件包括半导体衬底（30），相变材料图案（56），第一导电膜图案（52a）和第二导电膜图案（52b）。 相变材料图案设置在基板上。 第一导电膜图案被布置成与相变材料图案分开。 第二导电膜图案与第一导电膜图案的侧壁和相变材料图案接触。 在相变材料图案和第一导电膜图案之间施加缓冲图案（58）。 缓冲图案与第二导电膜图案的侧壁部分地接触。
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