公开(公告)号：KR1020000065599A

公开(公告)日：2000-11-15

申请号：KR1019990012025

申请日：1999-04-07

Applicant: 삼성전자주식회사

Inventor： 이헌규 ,  김종한 ,  최정혁

IPC: H01L27/115

Abstract: PURPOSE: A non-volatile memory device and a method for manufacturing the same are provided to prevent the growth of an uneven oxide layer between trapping sites and an insulating layer by forming an insulating layer on a peripheral area. CONSTITUTION: A non-volatile memory device comprises a first gate insulating layer and a second gate insulating layer. The first gate insulating layer is used for a memory cell device formed on a cell area. The second gate insulating layer is used for a memory cell drive device formed on a peripheral circuit area. A nitrogen atom is contained in the first and the second gate insulating layers. A method for manufacturing the same comprises the steps of: setting up a substrate(40) as a cell area and a peripheral circuit area; setting up the peripheral circuit area as an area for forming a high voltage transistor and an area for forming a low voltage transistor; forming a first gate insulating layer on the area for forming the high voltage transistor; and forming a second gate insulating layer on the cell area.

Abstract translation: 目的：提供一种非易失性存储器件及其制造方法，以通过在周边区域上形成绝缘层来防止捕获部位与绝缘层之间的不均匀氧化物层的生长。 构成：非易失性存储器件包括第一栅极绝缘层和第二栅极绝缘层。 第一栅极绝缘层用于形成在电池区域上的存储单元装置。 第二栅极绝缘层用于形成在外围电路区域上的存储单元驱动装置。 在第一和第二栅极绝缘层中含有氮原子。 其制造方法包括以下步骤：将衬底（40）设置为单元区域和外围电路区域; 将外围电路区域设置为用于形成高压晶体管的区域和用于形成低压晶体管的区域; 在用于形成高压晶体管的区域上形成第一栅极绝缘层; 以及在所述电池区域上形成第二栅极绝缘层。

公开(公告)号：KR100263063B1

公开(公告)日：2000-08-01

申请号：KR1019970055299

申请日：1997-10-27

Applicant: 삼성전자주식회사

Inventor： 이헌규 ,  최정혁

IPC: H01L27/085

Abstract: PURPOSE: A method for fabricating a CMOS transistor is provided to simplify a fabrication process, and to obtain a desired threshold voltage of each PMOS transistor by assuring a junction overlap region sufficiently of the PMOS transistor as adopting an LDD(Lightly Doped Drain) junction structure. CONSTITUTION: According to the method of fabricating a PMOS transistor and an NMOS transistor on a P type silicon substrate(10), a gate(50) of the NMOS transistor is formed on the substrate and a gate(51) of the PMOS transistor is formed in an N-well(20). Then, an N-type impurity is lightly implanted to a drain and source region(30,31,32,33) of the transistors to form an LDD(Lightly Doped Drain). The first and the second insulation film(60,65) are deposited on an upper part of the gates and the ion-implanted regions. And, after forming a compound spacer(64) comprising the first and the second insulation film on a side wall of the gate of the NMOS transistor by covering the PMOS transistor and etching back the region of the NMOS transistor, an N-type impurity is heavily implanted to form an LDD of the NMOS transistor. Then, after forming a spacer(64) comprising the first insulation film on a side wall of the gate of the PMOS transistor by covering the region of the NMOS transistor and etching back the first insulation film in the region of the PMOS transistor, a P-type impurity is heavily implanted to form an LDD of the PMOS transistor. Thus, a transistor is completed where the sizes of junction overlap regions are different according to the width of the spacers, by opening the region of the NMOS transistor and performing a thermal annealing.

Abstract translation: 目的：提供一种用于制造CMOS晶体管的方法，以简化制造工艺，并通过确保PMOS晶体管的结重叠区域采用LDD（轻掺杂漏极）结结构，从而获得每个PMOS晶体管的期望阈值电压 。 构成：根据在P型硅衬底（10）上制造PMOS晶体管和NMOS晶体管的方法，在衬底上形成NMOS晶体管的栅极（50），并且PMOS晶体管的栅极（51）为 形成在N阱（20）中。 然后，将N型杂质轻微地注入晶体管的漏极和源极区（30,31,32,33）以形成LDD（轻掺杂漏极）。 第一和第二绝缘膜（60,65）沉积在栅极的上部和离子注入区域上。 并且，在通过覆盖PMOS晶体管并蚀刻NMOS晶体管的区域，在NMOS晶体管的栅极的侧壁上形成包括第一和第二绝缘膜的复合间隔物（64）之后，N型杂质为 大量注入以形成NMOS晶体管的LDD。 然后，通过覆盖NMOS晶体管的区域并在PMOS晶体管的区域中蚀刻第一绝缘膜，在PMOS晶体管的栅极的侧壁上形成包括第一绝缘膜的间隔物（64）之后，将P 大量注入型杂质以形成PMOS晶体管的LDD。 因此，通过打开NMOS晶体管的区域并执行热退火，完成晶体管，其中结重叠区域的尺寸根据间隔物的宽度而不同。

公开(公告)号：KR1019990033864A

公开(公告)日：1999-05-15

申请号：KR1019970055299

申请日：1997-10-27

Applicant: 삼성전자주식회사

Inventor： 이헌규 ,  최정혁

IPC: H01L27/085

Abstract: 개선된 씨모오스 트랜지스터의 구조는, 제2도전형 MOS 트랜지스터의 게이트의 측벽에 형성되고 제1,2절연막으로 이루어진 복합스페이서와; 제1도전형 MOS 트랜지스터의 게이트의 측벽에 형성되고 상기 제1절연막으로 이루어진 스페이서와; 상기 게이트들의 하부에서 상기 게이트들과 각기 중첩되는 접합 오버랩 영역의 사이즈가 서로 다르게 형성된 드레인 영역들을 LDD구조로서 가짐을 특징으로 한다.

公开(公告)号：KR1020170142774A

公开(公告)日：2017-12-28

申请号：KR1020160076838

申请日：2016-06-20

Applicant: 삼성전자주식회사

Inventor： 강신환 ,  이재덕 ,  이헌규 ,  카나모리코지 ,  김광수 ,  장재훈

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/04 ,  H01L29/16

Abstract: 본발명의기술적사상은수직형메모리소자의기판콘택구조를변경하여공정난이도가하향되면서도고집적화및 신뢰성이향상된수직형비휘발성메모리소자및 그제조방법을제공한다. 그수직형비휘발성메모리소자는메모리셀들을구성하는수직채널층이기판상에형성된하부배선패턴을통해기판과전기적으로연결되는구조를가짐으로써, 기존의 VNAND에서수행되는수직채널층을기판에연결하기위한 SEG(Selective Epitaxial Growth) 공정, 및채널홀 바닥면의게이트유전체층을식각하는공정이생략될수 있다. 따라서, 공정난이도하향에따른제조비용이감소하고고집적화및 신뢰성이향상된수직형비휘발성메모리소자를구현할수 있도록한다.

Abstract translation: 本发明的技术特征提供了一个过程，同时改变具有改进的可靠性和高集成向下垂直hyeongbi性存储装置及其制造的方法的垂直型存储装置的基板接触结构的难度。 垂直hyeongbi性存储装置是通过使用在其上形成下布线图案是构成存储单元的垂直沟道底板具有连接到基底上并电连接至所述垂直沟道层在常规VNAND基板被进行了结构 可以省略SEG（选择性外延生长）工艺以及蚀刻沟道孔底部的栅极电介质层的工艺。 因此，根据工艺难度的降低，制造成本降低，并且实现了具有改进的集成度和可靠性的垂直型易失性存储器件。

公开(公告)号：KR1020170036877A

公开(公告)日：2017-04-03

申请号：KR1020150132515

申请日：2015-09-18

Applicant: 삼성전자주식회사

Inventor： 이창현 ,  이헌규 ,  강신환 ,  박영우

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573

Abstract: 3차원반도체메모리장치가제공된다. 3차원반도체메모리장치는기판상에수직적으로적층된전극들을포함하는적층구조체; 상기전극들과결합하여 3차원적으로배열된복수개의메모리셀들을구성하는하나의채널구조체로서, 상기채널구조체는상기적층구조체를관통하는복수개의수직채널들및 더미수직채널들과, 상기적층구조체아래에서상기복수개의수직채널들및 상기더미수직채널들을수평적으로연결하는제 1 수평채널을포함하는것; 및상기채널구조체의상기제 1 수평채널의측벽과연결된제 1 도전형의제 2 수평채널; 및상기더미수직채널들상단에제 2 도전형의도전플러그들을포함한다.

Abstract translation: 提供了一种三维半导体存储器件。 一种三维半导体存储器件包括：在衬底上包括垂直堆叠的电极的堆叠结构; 其中，沟道结构包括多个垂直沟道和穿过堆叠结构的伪垂直沟道，以及布置在堆叠结构中的多个存储单元， 以及第一水平通道，水平地连接所述多个竖直通道和下面的虚拟竖直通道; 以及耦合到沟道结构的第一水平沟道的侧壁的第一导电类型的第二水平沟道; 第二导电类型的导电插头位于伪垂直通道的顶部。

公开(公告)号：KR1020080053784A

公开(公告)日：2008-06-16

申请号：KR1020060125735

申请日：2006-12-11

Applicant: 삼성전자주식회사

Inventor： 이봉용 ,  이헌규 ,  김광수 ,  권상열

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: G11C29/808 ,  G11C29/846 ,  H01L27/2463

Abstract: A semiconductor memory device and a method for repairing the same are provided to improve a yield thereof by arranging high-performance cells in a redundancy cell array region. A main cell array region(100) includes a plurality of main bit lines. A first redundancy cell array region(210) having a first redundancy bit line is formed at one side of the main cell array region. A first dummy cell array region(310) having first dummy bit lines(DBL1) is formed at one side of the main cell array region. A second redundancy cell array region(220) having a second redundancy bit line is formed at the other side of the main cell array region. A second dummy cell array region(320) having second dummy bit lines(DBL2) is formed at the other side of the main cell array region. The first and second redundancy cell array regions are arranged near to the main cell array region in comparison with the first and second dummy cell array regions.

Abstract translation: 提供半导体存储器件及其修复方法，以通过在冗余单元阵列区域中布置高性能单元来提高其产量。 主单元阵列区域（100）包括多个主位线。 具有第一冗余位线的第一冗余单元阵列区域（210）形成在主单元阵列区域的一侧。 具有第一虚拟位线（DBL1）的第一虚拟单元阵列区域（310）形成在主单元阵列区域的一侧。 具有第二冗余位线的第二冗余单元阵列区域（220）形成在主单元阵列区域的另一侧。 具有第二虚拟位线（DBL2）的第二虚拟单元阵列区域（320）形成在主单元阵列区域的另一侧。 与第一和第二虚拟单元阵列区域相比，第一和第二冗余单元阵列区域布置在主单元阵列区域附近。

公开(公告)号：KR1020010055879A

公开(公告)日：2001-07-04

申请号：KR1019990057202

申请日：1999-12-13

Applicant: 삼성전자주식회사

Inventor： 최용주 ,  이헌규

IPC: H01L27/115

Abstract: PURPOSE: A method for manufacturing NOR type flash memory device is provided to solve an inferiority contacted electrically with a floating gate of a common source line and a bitline pad or contacted electrically with a common source area and a common drain area of a common source line and bitline pad by forming continuously a barrier metal liner formed on the sidewall and bottom of a bitline and common source line contact hole, to entirely surround the bitline pad and common source line with the barrier metal liner. CONSTITUTION: A process forms a device isolation layer defining plural active areas in parallel to each other at a certain area of a substrate. The process forms multiple wordline patterns across the plural active areas and a common source area and limits a common drain area at the active area of the both side of each of the wordline patterns. The process forms a spacer at the sidewalls of the plural wordline patterns. The process forms sequentially a first and second interlayer dielectric layer on the spacer formed. The process forms a self-aligned type bitline pad contact hole exposing the common drain area by patterning the first and second interlayer dielectric layer, and simultaneously forms a self-aligned type common source line contact hole exposing the common source area and the device isolation layer adjacent thereto. The process forms a protecting layer having an etch selecting rate facing to a silicon oxide layer on the sidewall of the bitline pad contact hole and the common source line contact hole. The process forms the barrier metal layer and the bitline pad within the bitline pad contact hole surrounded by the protecting layer. The process forms the barrier metal layer and the common source line within the common source line contact hole surrounded by the protecting layer.

Abstract translation: 目的：提供一种用于制造NOR型闪速存储器件的方法，以解决与公共源极线和位线焊盘的浮动栅极电接触或与公共源极的公共源极区域和公共漏极区域电接触的劣势 和位线焊盘，其通过形成在位线和公共源极线接触孔的侧壁和底部上的阻挡金属衬垫，以与阻挡金属衬垫完全围绕位线焊盘和公共源极线。 构成：过程形成在衬底的特定区域上彼此平行地限定多个有源区的器件隔离层。 该过程在多个有效区域和公共源区域中形成多个字线图案，并且限制每个字线图案的两侧的有效区域处的公共漏极区域。 该过程在多个字线图案的侧壁处形成间隔物。 该工艺在所形成的间隔物上依次形成第一和第二层间介电层。 该工艺形成自对准型位线焊盘接触孔，通过图案化第一和第二层间电介质层来暴露公共漏极区，同时形成暴露公共源区和器件隔离层的自对准型公共源极接触孔 相邻。 该工艺形成保护层，其具有面向位线焊盘接触孔的侧壁上的氧化硅层的蚀刻选择速率和公共源极线接触孔。 该工艺形成由保护层包围的位线焊盘接触孔内的阻挡金属层和位线焊盘。 该过程在由保护层包围的公共源极线接触孔内形成阻挡金属层和公共源极线。

公开(公告)号：KR100247225B1

公开(公告)日：2000-03-15

申请号：KR1019970041865

申请日：1997-08-28

Applicant: 삼성전자주식회사

Inventor： 이헌규 ,  최정혁

IPC: H01L27/115

Abstract: 불휘발성 메모리 장치의 제조 방법이 개시되어 있다. 제1 도전형의 반도체 기판의 상부에 소자 분리막을 형성하여 상기 반도체 기판에 액티브 영역들을 형성한다. 상기 반도체 기판의 상부에 게이트 절연막 및 플로팅 게이트용 제1 도전층을 차례로 형성한다. 상기 액티브 영역 중 제1 도전형의 액티브 영역으로 형성될 부위에만 제1 도전형의 불순물을 이온주입하여 제1 도전형의 기판 콘택용 액티브 영역을 형성한다. 상기 결과물의 상부에 층간 유전막 및 컨트롤 게이트용 제2 도전층을 차례로 형성한다. 사진식각 공정으로 상기 제2 도전층, 층간 유전막 및 제1 도전층을 식각하여 플로팅 게이트와 컨트롤 게이트가 적층된 셀 게이트를 형성한다. 상기 제1 도전형의 기판 콘택용 액티브 영역을 마스킹한 후, 노출된 기판의 표면에 제2 도전형의 불순물을 이온주입하여 제2 도전형의 소오스/드레인 영역을 형성한다. 종래 방법에 비해 별도의 마스크를 추가하지 않고 p
+ 형 기판 콘택을 형성할 수 있으므로, NOR형 플래쉬 메모리 셀에 벌크 바이어스를 원할히 잡을 수 있다.

公开(公告)号：KR1020000008294A

公开(公告)日：2000-02-07

申请号：KR1019980028037

申请日：1998-07-11

Applicant: 삼성전자주식회사

Inventor： 이헌규 ,  최정혁

IPC: H01L21/8247

Abstract: PURPOSE: The method for a nor type flash memory device is provided. CONSTITUTION: A nor type flash memory has a several unit shells which has both a source and a drain formed at the area where a bit line meets a word line perpendicularly on a silicon board. The nor type flash memory has also a bit line contact which connects the drain and the bit line, a shell array part which connects a word line contact with the word line, a active contact which connects the silicon board to around the shell array part, and a peripheral circuit including a gate contact. The bit line contact on the shell array part is formed by using a mask different from the masks for the active contact, the word line contact, and the gate contact. The shell array part includes plug ions, and the bit line contact, the word line contact, the active contact and the gate contact include iron plug. As the bit line contact on the shell array part is formed independently from the active contact and the gate contact, the contacts are formed safely without the damage from etching.

Abstract translation: 目的：提供闪存设备的类型和类型的方法。 构成：A型闪存具有几个单元壳，它们在位于线路上垂直于字线的区域形成源极和漏极。 还有类型闪存还具有连接漏极和位线的位线接触，将字线接触与字线连接的外壳阵列部分，将硅板连接到外壳阵列部分的有源触点， 以及包括门接触的外围电路。 壳阵列部分上的位线接触是通过使用不同于有源触点，字线触点和栅极触点的掩模的掩模形成的。 外壳阵列部分包括插塞离子，位线接触，字线接触，有源触点和栅极触点包括铁插头。 由于外壳阵列部分上的位线接触独立于有源触点和栅极接触形成，触点形成安全，而不会受到蚀刻的损害。