公开(公告)号：KR1020130084029A

公开(公告)日：2013-07-24

申请号：KR1020120004714

申请日：2012-01-16

Applicant: 삼성전자주식회사

Inventor： 김형옥 ,  전재한 ,  최정연 ,  김기섭 ,  원효식

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5045 ,  G06F2217/84 ,  H01L27/0207

Abstract: PURPOSE: A design method of a system-on-chip including a tapless standard cell, a design system thereof, and a system-on-chip thereof are provided to increase the operation speed of a system-on-chip. CONSTITUTION: To reflect a first fast corner of the movement speed distribution to the reverse body biasing and change the first fast corner to a second fast corner, a second timing parameter corresponding to the second fast corner is set (S130). The second fast corner has a slower movement speed than the first fast corner. Based on a first timing parameter corresponding to a second slow corner and the second timing parameter corresponding to the second fast corner, a system-on-chip including a tapless standard cell is produced (S150). [Reference numerals] (AA) Start; (BB) Finish; (S110) Set a first timing parameter for increasing a slow corner by reflecting forward body biasing; (S130) Set a second timing parameter for decreasing a fast corner by reflecting reverse body biasing; (S150) Produce a system-on-chip based on the first and second timing parameters

Abstract translation: 目的：提供一种片上系统的设计方法，包括无无线标准单元，其设计系统及其片上系统，以提高片上系统的运行速度。 构成：为了将运动速度分布的第一快速角反映到反转体偏置并将第一快速拐角改变到第二快速拐角，设置对应于第二快速拐角的第二定时参数（S130）。 第二个快速拐角的移动速度比第一个快速转角慢。 基于对应于第二慢转角的第一定时参数和对应于第二快速转角的第二定时参数，产生包括无无线标准单元的片上系统（S150）。 （附图标记）（AA）开始; （BB）完成; （S110）设定第一定时参数，通过反射向前的主体偏置来增加慢转角; （S130）设置第二定时参数，通过反射反向偏置来减小快速转角; （S150）基于第一和第二定时参数生成片上系统

公开(公告)号：KR1020130076428A

公开(公告)日：2013-07-08

申请号：KR1020110145014

申请日：2011-12-28

Applicant: 삼성전자주식회사

Inventor： 전재한 ,  한호산

IPC: H01R13/62 ,  A61B8/00

CPC classification number: A61B8/44 ,  A61B8/4433

Abstract: PURPOSE: A connector for a probe and an ultrasound diagnosis apparatus adopting the same are provided to make a probe of an ultrasound diagnosis apparatus compact and slim, thereby improving portability. CONSTITUTION: A mail connector (200) is detachably coupled to a female connector, which is prepared in a main body of an ultrasound diagnosis apparatus. A plurality of first connection printed circuit boards (PCB) (230) is stacked and disposed in a state of being stood within a plurality of housings (210,280). Each of the plurality of first connection PCBs includes a plurality of signal pins and a substrate. The plurality of signal pins of each of the plurality of first connection PCBs contacts a plurality of pins of the female connector. The plurality of signal pins of each of the plurality of first connection PCBs is arranged in a row on the substrate. A first grounding pin is interposed between the plurality of signal pins.

Abstract translation: 目的：提供一种用于探针的连接器和采用该探针的超声诊断装置，以使得超声诊断装置的探针紧凑且纤细，从而提高便携性。 构成：邮件连接器（200）可拆卸地联接到在超声波诊断装置的主体中准备的阴连接器。 多个第一连接印刷电路板（PCB）（230）被堆叠并设置在处于多个壳体（210,280）内的状态。 多个第一连接PCB中的每一个包括多个信号引脚和基板。 多个第一连接PCB中的每一个的多个信号引脚接触阴连接器的多个引脚。 多个第一连接PCB中的每一个的多个信号引脚在衬底上排成一列。 第一接地引脚插在多个信号引脚之间。

公开(公告)号：KR1020090099846A

公开(公告)日：2009-09-23

申请号：KR1020080025055

申请日：2008-03-18

Applicant: 삼성전자주식회사

Inventor： 이봉현 ,  최정연 ,  전재한 ,  도경태

IPC: G11C7/22 ,  G11C7/24

CPC classification number: H04B15/02 ,  H04B2215/064 ,  G11C7/22 ,  G11C7/24 ,  H03K19/0016

Abstract: PURPOSE: A circuit of an active clock shielding structure is provided to use a power gating signal transmission line and/or retention signal transmission line as a shielding line by arranging the power gating signal transmission line and/or retention signal transmission line in parallel to a clock signal transmission line. CONSTITUTION: A circuit of an active clock shielding structure includes a logic circuit, a power gating circuit, a clock signal transmission line(260), at least power gating signal transmission line(280). The logic circuit receives a clock signal and performs a logic operation. The power gating circuit converts the logic circuit into an active mode or slip mode in response to the power gating signal. The clock signal transmission line transmits the clock signal. The power gating signal transmission lien transmits the power gating signal. The power gating signal transmission line operates with a pair of the shielding lines of the clock signal transmission line.

Abstract translation: 目的：提供有源时钟屏蔽结构的电路，通过将电源门控信号传输线路和/或保持信号传输线路平行布置为使用电源门控信号传输线路和/或保持信号传输线路作为屏蔽线路 时钟信号传输线。 构成：活动时钟屏蔽结构的电路包括至少电力门控信号传输线（280）的逻辑电路，电源门控电路，时钟信号传输线（260）。 逻辑电路接收时钟信号并进行逻辑运算。 电源门控电路响应于电源门控信号将逻辑电路转换成活动模式或滑移模式。 时钟信号传输线传输时钟信号。 电源门控信号传输留置权传输电源门控信号。 电源门控信号传输线与时钟信号传输线的一对屏蔽线一起工作。

公开(公告)号：KR1020140050151A

公开(公告)日：2014-04-29

申请号：KR1020120115554

申请日：2012-10-17

Applicant: 삼성전자주식회사 ,  한국과학기술원

Inventor： 서문준 ,  백돈규 ,  신영수 ,  신인섭 ,  김형옥 ,  오충기 ,  전재한 ,  도경태 ,  최정연

IPC: H01L21/00 ,  G06F17/50 ,  H01L21/66

CPC classification number: H01L21/67276 ,  G06F17/50 ,  H01L22/20

Abstract: The present invention relates to a modeling method which estimates delay time and output time of a gate when a body bias voltage is applied. A method of modeling the delay time or the output time of the gate according to the present invention includes a step of selecting a first gate among a plurality of gates; a step of determining the structure of the selected first gate; a step of generating the delay time ratio or the output time ratio of the selected first gate according to the determination result; and a step of calculating the delay time or the output time of a second gate when the body bias voltage is applied based on the delay time or the output time of the second gate among the generated delay time ratio or the output time ratio and the gates. [Reference numerals] (110) First delay time table; (120) Delay time ratio table; (130) Second delay time table

Abstract translation: 本发明涉及一种当施加人体偏置电压时估计门的延迟时间和输出时间的建模方法。 根据本发明的对门的延迟时间或输出时间建模的方法包括在多个门中选择第一门的步骤; 确定所选择的第一门的结构的步骤; 根据确定结果产生所选择的第一门的延迟时间比或输出时间比的步骤; 以及基于所生成的延迟时间比或输出时间比的延迟时间或第二栅极的输出时间来施加施加了体偏置电压时的第二栅极的延迟时间或输出时间的步骤， 。 （附图标记）（110）第一延迟时间表; （120）延迟时间比表; （130）第二延迟时间表

公开(公告)号：KR1020140015880A

公开(公告)日：2014-02-07

申请号：KR1020120081855

申请日：2012-07-26

Applicant: 삼성전자주식회사

Inventor： 김형옥 ,  김욱 ,  서문준 ,  오충기 ,  전재한 ,  도경태 ,  최정연 ,  원효식 ,  김기섭

IPC: G05F1/567

CPC classification number: G06F1/3206 ,  G05D23/1919 ,  G06F1/20 ,  G06F1/324 ,  Y02D10/126

Abstract: According to the present invention, a method for controlling the temperature of a semiconductor device includes a step of sensing the driving temperature of the semiconductor device, a step of controlling a body bias level for at least one functional block of the semiconductor device if the driving temperature satisfies a first condition, and a step of activating a thermal throttling operation and controlling the body bias level at the same time if the driving temperature satisfies a second condition. The thermal throttling operation controls the driving voltage and/or clock frequency of the at least one functional block of the semiconductor device.

Abstract translation: 根据本发明，一种用于控制半导体器件的温度的方法包括检测半导体器件的驱动温度的步骤，如果驱动器件对半导体器件的至少一个功能块进行器件偏置电平的控制， 温度满足第一条件，以及如果驱动温度满足第二条件，则激活热节流操作并同时控制身体偏置电平的步骤。 热节流操作控制半导体器件的至少一个功能块的驱动电压和/或时钟频率。