Abstract:
PURPOSE: Semiconductor device manufacturing equipment is provided to install a plurality of semiconductor fabrication apparatuses within a limited area by reducing an occupied area of various fabrication apparatuses within a production line. CONSTITUTION: A plurality of chambers are formed with a plurality of process chambers(32a), a plurality of load lock chambers(34a), and a plurality of auxiliary chambers. A transfer chamber(30a) has a robot device(Ra) for transferring a wafer(W). The process chamber(32a), the load lock chamber(34a), and the auxiliary chamber are selectively connected with the transfer chamber(30a). The process chamber(32a), the load lock chamber(34a), and the auxiliary chamber are vertically arrayed on the basis of the transfer chamber(30a). Various units(38a) such as vacuum lines and gas supply lines connected with each chamber are arrayed to the vertical direction.
Abstract:
PURPOSE: A shower head for fabricating a semiconductor is provided to decrease the number of particles dropped to a wafer, by performing an embossing process regarding the surface of a spraying plate for spraying metallic gas so that the surface area where the metallic gas is attached is increased. CONSTITUTION: A shower head body has a buffer space part to which process gas is induced. A spraying plate(23) sprays the process gas in the buffer space part, installed on the bottom surface of the shower head body. The surface of the spraying plate becomes rough to increase the surface area to which the metallic gas is attached. The surface of the spraying plate is embossed.
Abstract:
A diagnostic system (10) in an engine management system is provided for generating a diagnostic trouble code (DTC) to indicate the operational status of a component or a sub-system. The diagnostic system includes a diagnostic function module (DF Module) (20, 20', 20'') for each DTC or a group of related DTCs associated with a component or sub-system. The DF module includes means (22) for executing an evaluation routine to evaluate a component/sub- system to which the DTC of the specific DF module relates, and a dynamic scheduler (30) for determining which DF module may be allowed to execute an evaluation routine at a particular time. Each DF module (20, 20', 20'') includes means (22) for producing a ranking value dependent on the operating status of the component or sub-system being evaluated, a ranking value being generated each time an evaluation routine is performed; means (23) for processing and storing statistical results of the ranking values obtained over a number of evaluation routines; means (23) for evaluating the statistical results to produce evaluated data in the form of either an evaluated no-fault signal or an evaluated fault signal, and means (24) for establishing the priority of the associated evaluation routine, and means for transmitting the evaluated signals to the dynamic scheduler (30).
Abstract:
PURPOSE: A color standardization method of a graphic user interface(GUI) for semiconductor fabrication facilities is provided to permit an immediate grasp of a process proceeding state in the facilities and thereby to allow an improvement in productivity. CONSTITUTION: In the color standardization method, colors displayed on the graphic user interface(GUI) are classified by the facilities, wafers, and causes of alarm. In classification of colors by the facilities, the color of a cassette depends on whether the cassette is in a load lock chamber or not, and the color of the load lock chamber depends on whether a process chamber can be used or not. The color of the load lock chamber further depends on whether a door thereof can be promptly opened or not. In classification of colors by the wafers, the color of the wafer depends on whether a deposition process has already been performed, is being performed, will be performed, or is stopped. In addition, the color of the wafer is classified by depending on caused of alarm, such as pressure, temperature, or mass flow controller.
Abstract:
PURPOSE: A gate having an expanded upper area and a method for fabricating a semiconductor device having the same are provided to increase an upper area of a gate electrode by forming a wing portion on a lateral portion of an upper part of a gate poly. CONSTITUTION: The first insulating layer(12) is formed on a semiconductor substrate(10). A gate pattern(14) is formed on the semiconductor substrate. The second insulating layer is formed on the gate pattern and the semiconductor substrate. An upper surface of the second insulating layer is formed under the upper surface of the gate pattern by removing the second insulating layer. A conductive layer is formed on the second insulating layer and the upper surface of the gate pattern. A spacer(19) is formed on a lateral portion of an upper part of the gate pattern. The second insulating layer is removed therefrom.
Abstract:
PURPOSE: An apparatus for eliminating residual gas of a gas supplying apparatus is provided to prevent WF6 gas remaining in a gas line from being injected to the inside of a chamber together with carrier gas like argon, by supplying the WF6 gas to the chamber in a main deposition step and by eliminating the WF6 gas remaining in the gas line connected to a low stress valve. CONSTITUTION: The low stress valve(100) supplies or intercepts the gas supplied from a plurality of mass flow controllers(MFC's)(60) through the gas line(81). A WF6 gas eliminating unit eliminates the remaining WF6 gas in the gas line connected to a gas introducing line of the low stress valve.
Abstract:
공정 불량 발생을 억제하여 반도체 소자의 신뢰성 향상을 꾀할 수 있도록 한 반도체 소자의 다층 배선 형성방법이 개시된다. 제 1 층간 절연막이 구비된 반도체 기판 상에 제 1 도전성막과 제 2 도전성막을 순차적으로 형성하고, 콜리메이터가 구비된 스퍼터 장치를 이용하여 제 2 도전성막 상에 Ti/TiN 적층막 구조의 반사방지막을 형성한 다음, 제 1 층간 절연막의 표면이 소정 부분 노출되도록 반사방지막과 제 2 및 제 1 도전성막을 소정 부분 선택식각하여, 제 2 도전성막을 사이에 두고 그 상·하측부에 반사방지막과 제 1 도전성막이 놓여진 구조의 금속 배선을 형성한다. 상기 결과물 전면에 제 2 층간 절연막을 형성하고, 금속 배선의 표면이 소정 부분 노출되도록 제 2 층간 절연막과 반사방지막을 소정 부분 건식식각하여 비어 홀을 형성하되, 그 바텀면의 가장자리부를 따라서는 테이퍼진 형상의 반사방지막이 잔존되도록 한다. 폴리머 제거용 습식식각을 실시한 뒤, RF 스퍼터 식각을 실시하여 금속 배선의 표면 노출부에 형성된 자연 산화막과 반사방지막의 테이퍼진 부분을 제거한 다음, 비어 홀 내부에 도전성 플러그를 형성한다. 그 결과, 비어 홀 형성시 야기되는 공정 불량(예컨대, 비어 홀 하단의 반사방지막 안쪽으로 오목한 형상의 골이 형성되는 불량이나 비어 홀 내에 셔도우 포인트가 생성되는 불량)을 제거할 수 있게 되므로, 반도체 소자의 신뢰성을 향상시킬 수 있게 된다.