公开(公告)号：KR1020090113621A

公开(公告)日：2009-11-02

申请号：KR1020080039432

申请日：2008-04-28

Applicant: 성균관대학교산학협력단

Inventor： 이내응 ,  문학기 ,  김선일

IPC: H01L21/28

CPC classification number: H01L21/76877 ,  H01L21/28556 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/76846

Abstract: PURPOSE: A method for fabricating metal line using deposition and etching process in semiconductor device to obtain uniform deposition are provided to secure the reliability of the metal wiring and semiconductor device. CONSTITUTION: The insulating layer(110) is formed on the semiconductor substrate(100) having an infrastructure. The trench or the via hall of the constant pattern is formed on the insulating layer. The deposition process for conducting material is performed on the semiconductor substrate in which the trench or the via hole is formed. The etching process for the deposition material evaporated on the semiconductor substrate is performed. The conductive layer is formed in to fill the trench or the via hole with the conducting material. The metal wiring(150d) is formed to removes the conductive layer.

Abstract translation: 目的：提供一种在半导体器件中使用沉积和蚀刻工艺制造金属线以获得均匀沉积的方法，以确保金属布线和半导体器件的可靠性。 构成：在具有基础设施的半导体衬底（100）上形成绝缘层（110）。 在绝缘层上形成恒定图案的沟槽或通孔室。 在形成沟槽或通孔的半导体衬底上进行用于导电材料的沉积工艺。 执行在半导体衬底上蒸发的沉积材料的蚀刻工艺。 导电层形成为用导电材料填充沟槽或通孔。 金属布线（150d）被形成以去除导电层。