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公开(公告)号：KR101069630B1
公开(公告)日：2011-10-05
申请号：KR1020080039447
申请日：2008-04-28
Applicant: 성균관대학교산학협력단
IPC: H01L21/28
Abstract: 본발명은흡착억제제를이용한반도체소자의금속배선형성방법에관한것으로, 본발명에따른반도체소자의금속배선형성방법은, 하부구조가형성된반도체기판상에절연층을형성하고, 상기절연층상에일정패턴의트렌치(trench) 또는비아(via)홀을형성하는단계와; 상기트렌치또는비아홀이형성된반도체기판상에, 상기도전물질의증착을위한증착공정과상기도전물질의흡착을억제하기위한흡착억제공정을, 상기트렌치또는비아홀이상기도전물질로채워질때까지연속적, 단계적, 순환적방법중에서선택된적어도어느하나의방법으로수행하여도전층을형성하는단계와; 상기절연층의상부가노출될때까지상기도전층제거공정을수행하여상기트렌치또는비아홀을제외한부분의도전층을제거함에의해금속배선을형성하는단계를구비한다. 본발명에따르면, 금속배선형성시보이드나연결선없는균일한증착이가능한장점이있다.
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公开(公告)号：KR1020090084236A
公开(公告)日：2009-08-05
申请号：KR1020080010291
申请日：2008-01-31
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
Abstract: A memory chip array is provided to reduce the whole size by arranging a circuit related to column operation such as a sense amplifier and a column decoder. A memory chip array comprises a plurality of cell arrays(20) and a row decoder. The row decoder comprises a low select(22) and a pre-decoder(21), and the low select is formed in one-side of each cell array. A plurality of cell arrays are connected to pre-decoder in common, and the sense amplifier and the column decoder(23) are formed in the lower-part of each cell array.
Abstract translation: 提供存储器芯片阵列以通过布置与诸如读出放大器和列解码器的列操作相关的电路来减小整体尺寸。 存储芯片阵列包括多个单元阵列（20）和行解码器。 行解码器包括低选择（22）和预解码器（21），并且低选择形成在每个单元阵列的一侧。 多个单元阵列共同连接到预解码器，并且读出放大器和列解码器（23）形成在每个单元阵列的下部。
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3.发明授权유기-무기 나노 복합 절연층을 포함하여 이루어진 유기물반도체 소자, 유기-무기 나노 복합 절연체 용액 및 이들의제조 방법 失效有机无机纳米复合介电层的有机半导体器件，有机无机纳米复合电介质溶液及其方法
公开(公告)号：KR100878225B1
公开(公告)日：2009-01-13
申请号：KR1020070078667
申请日：2007-08-06
Applicant: 성균관대학교산학협력단
Abstract: An organic semiconductor device comprising organic-inorganic nano-composite dielectric layer is provided to realize excellent flexibility, low leakage current, high dielectric constant by using the organic-inorganic nano complex insulating layer. In an organic semiconductor device, a seed layer(30) is formed at the upper part of the substrate(10). A gate electrode(50) is formed on the seed layer. An organic-inorganic nano complex insulating layer(60) is formed on the substrate in which the gate electrode is formed. An organic semiconductor layer(70) is formed on the dielectric layer, and a source/drain electrode layer(80) is formed. The inorganic oxide dispersion solution is manufactured by mixing the inorganic oxide nano particle with the acid solvent and coupling agent. An organic-inorganic oxides nano composite solution is manufactured by mixing the inorganic oxide dispersion solution with the organic compound insulator. The organic-inorganic oxide cargo nano composite solution is coated on substrate.
Abstract translation: 提供有机无机纳米复合电介质层的有机半导体器件，通过使用有机 - 无机纳米复合绝缘层实现优异的柔性，低漏电流，高介电常数。 在有机半导体装置中，在基板（10）的上部形成种子层（30）。 在种子层上形成栅电极（50）。 在形成有栅电极的基板上形成有机 - 无机纳米复合绝缘层（60）。 在电介质层上形成有机半导体层（70），形成源极/漏极层（80）。 无机氧化物分散液通过将无机氧化物纳米粒子与酸性溶剂和偶联剂混合来制造。 通过将无机氧化物分散液与有机化合物绝缘体混合来制造有机 - 无机氧化物纳米复合物溶液。 将有机 - 无机氧化物载体纳米复合物溶液涂覆在基材上。
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公开(公告)号：KR1020100061064A
公开(公告)日：2010-06-07
申请号：KR1020080119942
申请日：2008-11-28
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L29/786
CPC classification number: H01L27/1225 , H01L21/8238 , H01L27/092 , H01L27/1251
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to easily form as a low-temperature process by forming a first oxide channel layer and a second oxide channel layer into an oxide. CONSTITUTION: A first thin film transistor includes a first source(S10), a first drain, a first channel layer, and a first gate. A second thin film transistor includes a second source(S20), a second drain, a second channel layer, and a second gate. One is a p-type oxide layer among the first and the second channel layer. The first and the second thin film transistor is a bottom gate(BG10, BG20) structure or a top gate structure. One is a dual gate including more other gates among the first and the second thin film transistor at least.
Abstract translation: 目的：通过将第一氧化物沟道层和第二氧化物沟道层形成为氧化物，提供半导体器件及其制造方法以容易地形成为低温工艺。 构成：第一薄膜晶体管包括第一源（S10），第一漏极，第一沟道层和第一栅极。 第二薄膜晶体管包括第二源（S20），第二漏极，第二沟道层和第二栅极。 一个是第一和第二沟道层中的p型氧化物层。 第一和第二薄膜晶体管是底栅（BG10，BG20）结构或顶栅结构。 一个是至少包括第一和第二薄膜晶体管中的更多其它栅极的双栅极。
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公开(公告)号：KR1020090113633A
公开(公告)日：2009-11-02
申请号：KR1020080039447
申请日：2008-04-28
Applicant: 성균관대학교산학협력단
IPC: H01L21/28
CPC classification number: H01L21/76877 , H01L21/28556 , H01L21/3212 , H01L21/76846
Abstract: PURPOSE: A method for fabricating metal line using adsorption inhibitor in semiconductor device is provided to secure the reliability of the metal wiring and semiconductor device. CONSTITUTION: The insulating layer(110) is formed on the semiconductor substrate(100). The trench or the via hall of the constant pattern is formed on the insulating layer. The deposition process for the conducting material is performed. The adsorption suppression process for restraining the adsorption of the conducting material is performed. The process of removing the conductive layer is performed to expose the insulating layer. The metal wiring(150c) is formed by removing the conductive layer.
Abstract translation: 目的：提供一种在半导体器件中使用吸附抑制剂制造金属线的方法，以确保金属布线和半导体器件的可靠性。 构成：绝缘层（110）形成在半导体衬底（100）上。 在绝缘层上形成恒定图案的沟槽或通孔室。 执行导电材料的沉积工艺。 执行用于抑制导电材料的吸附的吸附抑制过程。 执行去除导电层的过程以暴露绝缘层。 通过去除导电层来形成金属布线（150c）。
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Patent Agency Ranking
公开(公告)号：KR101413658B1
公开(公告)日：2014-07-07
申请号：KR1020090038461
申请日：2009-04-30
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L29/786
Abstract: 반도체 소자 및 그 제조방법에 관해 개시되어 있다. 개시된 반도체 소자는 p형 산화물 박막트랜지스터 및 n형 산화물 박막트랜지스터를 포함하는 상보성(complementary) 소자일 수 있다. 예컨대, 개시된 반도체 소자는 인버터(inverter), NAND 소자, NOR 소자 등과 같은 논리소자일 수 있다.
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公开(公告)号：KR101413657B1
公开(公告)日：2014-07-02
申请号：KR1020080119942
申请日：2008-11-28
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L29/786
Abstract: 반도체 소자 및 그 제조방법에 관해 개시되어 있다. 개시된 반도체 소자는 p형 산화물 박막트랜지스터 및 n형 산화물 박막트랜지스터를 포함하는 상보성(complementary) 소자일 수 있다. 예컨대, 개시된 반도체 소자는 인버터(inverter), NAND 소자, NOR 소자 등과 같은 논리소자일 수 있다.
Abstract translation: 公开了一种半导体器件及其制造方法。 所公开的半导体器件可以是包括p型氧化物薄膜晶体管和n型氧化物薄膜晶体管的互补装置。 例如，所公开的半导体器件可以是诸如反相器，NAND器件，NOR器件等的逻辑器件。
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公开(公告)号：KR1020100038986A
公开(公告)日：2010-04-15
申请号：KR1020080098170
申请日：2008-10-07
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
CPC classification number: G11C13/00 , G11C5/02 , G11C13/0023 , G11C2213/71 , G11C2213/77 , H01L27/0688 , H01L27/1021 , H01L27/1052 , H01L27/1225 , H01L29/7869
Abstract: PURPOSE: A stack memory device including an oxide thin film transistor is provided to improve integration by minimizing an area of an active circuit unit even through the stacked memory layer increases. CONSTITUTION: A stack memory device includes an active circuit unit(10), a row line(12), and a column line(14). The low line and the column line are electrically connected to the active circuit. A selection transistor is formed on the same plane on the one end of the row line and column line of the memory array.
Abstract translation: 目的：提供包括氧化物薄膜晶体管的堆叠存储器件，以便即使通过堆叠的存储层增加，也可以通过使有源电路单元的面积最小化来提高积分。 构成：堆叠存储器件包括有源电路单元（10），行线（12）和列线（14）。 低线和列线电连接到有源电路。 选择晶体管形成在存储器阵列的行线和列线的一端的同一平面上。
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公开(公告)号：KR1020100061290A
公开(公告)日：2010-06-07
申请号：KR1020090038461
申请日：2009-04-30
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L29/786
CPC classification number: H01L27/1225 , H01L27/092 , H01L27/1251
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve a performance characteristic of the device by reducing a resistance with forming a p+ domain on the central part of a first oxide channel layer. CONSTITUTION: A first oxide channel layer(C10) is formed into a first conductive type oxide on a lower part layer. A first electrode layer covering the first channel layer is formed on the lower part layer. The first electrode layer and a second electrode layer separated are formed. A second oxide channel layer(C20) is formed into a second conductive type oxide on the lower part later. The first electrode layer is patterned. A first source, a first drain and the second drain are formed by the patterning of the first electrode layer.
Abstract translation: 目的：提供半导体器件及其制造方法，以通过在第一氧化物沟道层的中心部分形成p +畴来降低电阻来提高器件的性能特性。 构成：第一氧化物沟道层（C10）在下部层上形成为第一导电型氧化物。 覆盖第一沟道层的第一电极层形成在下部层上。 形成分离的第一电极层和第二电极层。 第二氧化物沟道层（C20）稍后在下部形成第二导电型氧化物。 图案化第一电极层。 通过图案化第一电极层形成第一源极，第一漏极和第二漏极。
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公开(公告)号：KR1020100040580A
公开(公告)日：2010-04-20
申请号：KR1020080099778
申请日：2008-10-10
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L21/8239
CPC classification number: G11C5/02 , G11C5/143 , G11C7/18 , G11C8/12 , G11C13/0023 , G11C2213/71
Abstract: PURPOSE: A stacked memory device is provided to reduce the area in which the stacked memory device is occupied by stacking active circuit parts between memory layers. CONSTITUTION: Stacked memory layers(110) include memory cell array. A first active circuit part(140) processes the address information of the memory cell array which is divided into vertical address information and horizontal address information. A second active circuit part(160) is arranged on the first active circuit part. The second active circuit part generates memory selection signal to each memory cell based on the processed signal of the first active circuit parts. The first active circuit part includes a level decoder(120) and a pre decoder(130). The level decoder decodes the vertical address information. The pre decoder decodes the horizontal address information.
Abstract translation: 目的：提供堆叠的存储器件，以通过在存储器层之间堆叠有源电路部分来减少堆叠的存储器件被占用的区域。 构成：堆叠的存储器层（110）包括存储单元阵列。 第一有源电路部分（140）处理被划分为垂直地址信息和水平地址信息的存储单元阵列的地址信息。 第二有源电路部分（160）布置在第一有源电路部分上。 第二有源电路部分基于第一有源电路部分的处理信号，向每个存储器单元产生存储器选择信号。 第一有源电路部分包括电平解码器（120）和预解码器（130）。 电平解码器解码垂直地址信息。 预解码器解码水平地址信息。
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