公开(公告)号：KR1020110123633A

公开(公告)日：2011-11-15

申请号：KR1020100043226

申请日：2010-05-07

Applicant: 성균관대학교산학협력단

Inventor： 이내응 ,  문학기

IPC: H01L21/205 ,  C23C16/00 ,  C23C16/06 ,  H01L21/28

CPC classification number: H01L21/28556 ,  H01L21/02046 ,  H01L21/02178 ,  H01L21/324

Abstract: PURPOSE: A copper alloy formation method which uses cyclic deposition processes is provided to adjust alloy element content within copper, thereby improving commercial applications of a copper alloy. CONSTITUTION: A copper layer is evaporated using a copper precursor on a substrate placed within a chamber. A surface processing process is performed with hydrogen gas or hydrogen plasma. A purging process is performed using an inert gas. An alloy element layer is evaporated using the precursor including alloy elements on the copper layer arranged on the substrate. The surface processing process and purging process are repeated. A multi-layered thin film made of copper and alloying elements is arranged. The multi-layered thin film is heat-treated.

Abstract translation: 目的：提供使用循环沉积工艺的铜合金形成方法来调节铜中的合金元素含量，从而改善铜合金的商业应用。 构成：在放置在室内的基板上使用铜前体蒸发铜层。 用氢气或氢等离子体进行表面处理。 使用惰性气体进行净化处理。 使用包含合金元素的前体在布置在基板上的铜层上蒸发合金元素层。 重复表面处理过程和清洗过程。 布置由铜和合金元素制成的多层薄膜。 多层薄膜进行热处理。

公开(公告)号：KR1020090113621A

公开(公告)日：2009-11-02

申请号：KR1020080039432

申请日：2008-04-28

Applicant: 성균관대학교산학협력단

Inventor： 이내응 ,  문학기 ,  김선일

IPC: H01L21/28

CPC classification number: H01L21/76877 ,  H01L21/28556 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/76846

Abstract: PURPOSE: A method for fabricating metal line using deposition and etching process in semiconductor device to obtain uniform deposition are provided to secure the reliability of the metal wiring and semiconductor device. CONSTITUTION: The insulating layer(110) is formed on the semiconductor substrate(100) having an infrastructure. The trench or the via hall of the constant pattern is formed on the insulating layer. The deposition process for conducting material is performed on the semiconductor substrate in which the trench or the via hole is formed. The etching process for the deposition material evaporated on the semiconductor substrate is performed. The conductive layer is formed in to fill the trench or the via hole with the conducting material. The metal wiring(150d) is formed to removes the conductive layer.

Abstract translation: 目的：提供一种在半导体器件中使用沉积和蚀刻工艺制造金属线以获得均匀沉积的方法，以确保金属布线和半导体器件的可靠性。 构成：在具有基础设施的半导体衬底（100）上形成绝缘层（110）。 在绝缘层上形成恒定图案的沟槽或通孔室。 在形成沟槽或通孔的半导体衬底上进行用于导电材料的沉积工艺。 执行在半导体衬底上蒸发的沉积材料的蚀刻工艺。 导电层形成为用导电材料填充沟槽或通孔。 金属布线（150d）被形成以去除导电层。

公开(公告)号：KR1020110123631A

公开(公告)日：2011-11-15

申请号：KR1020100043224

申请日：2010-05-07

Applicant: 성균관대학교산학협력단

Inventor： 이내응 ,  문학기

IPC: C23C16/06 ,  C23C16/513 ,  H01L21/205

CPC classification number: C23C16/452 ,  C23C16/06

Abstract: PURPOSE: A method of formation to copper alloys using plasma-enhanced chemical vapor deposition is provided to simultaneously evaporate copper and alloying elements by restricting abnormal reaction between the alloying elements and copper. CONSTITUTION: A method of formation to copper alloys using plasma-enhanced chemical vapor deposition comprises next steps. An evaporation object is included in a chamber(100). Each one end of first and second nozzles(310,320) is connected with first and second precursor supplying devices. The copper precursor and alloying element precursor are supplied into the chamber. Plasma is generated outside of the chamber. The alloying element precursor comprises aluminum precursor. Carrying gas, transporting the precursor, comprises hydrogen.

Abstract translation: 目的：提供使用等离子体增强化学气相沉积法形成铜合金的方法，通过限制合金元素和铜之间的异常反应来同时蒸发铜和合金元素。 构成：使用等离子体增强化学气相沉积法形成铜合金的方法包括以下步骤。 蒸发对象包括在腔室（100）中。 第一和第二喷嘴（310,320）的每一端与第一和第二前体供应装置连接。 将铜前体和合金元素前体供应到室中。 在室外产生等离子体。 合金元素前体包括铝前体。 运送前体的携带气体包括氢气。

公开(公告)号：KR101685372B1

公开(公告)日：2016-12-12

申请号：KR1020100043226

申请日：2010-05-07

Applicant: 성균관대학교산학협력단

Inventor： 이내응 ,  문학기

IPC: H01L21/205 ,  C23C16/00 ,  C23C16/06 ,  H01L21/28

Abstract: 본발명은챔버내에배치된기판상에구리전구체를사용하여구리층을증착한후 비활성기체를이용하여퍼징하고, 수소기체또는수소플라즈마로표면처리하는단계; 및상기기판상에형성된구리층에합금원소를포함하는전구체를사용하여합금원소층을증착한후 비활성기체를이용하여퍼징하고, 수소기체또는수소플라즈마로표면처리하는단계를포함하는순환주기를반복하여수행한후 열처리하는것을특징으로하는, 순환적증착을이용한구리합금형성방법에관한것이다. 본발명은산소나플로린원자를포함하는구리전구체를사용하면서도구리내 합금원소의함유량을조절할수 있는구리합금형성방법을제공함으로써물성이우수한구리합금의상업적활용도를높일수 있다.

Abstract translation: 目的：提供使用循环沉积工艺的铜合金形成方法来调节铜中的合金元素含量，从而改善铜合金的商业应用。 构成：在放置在室内的基板上使用铜前体蒸发铜层。 用氢气或氢等离子体进行表面处理。 使用惰性气体进行净化处理。 使用包含合金元素的前体在布置在基板上的铜层上蒸发合金元素层。 重复表面处理过程和清洗过程。 布置由铜和合金元素制成的多层薄膜。 多层薄膜进行热处理。

公开(公告)号：KR1020110123634A

公开(公告)日：2011-11-15

申请号：KR1020100043227

申请日：2010-05-07

Applicant: 성균관대학교산학협력단

Inventor： 이내응 ,  문학기

IPC: H01L21/28

CPC classification number: H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76877

Abstract: PURPOSE: A wiring formation method of a semiconductor device by an ion injection method is provided to uniformly evaporate a conductive layer from the floor of a trench to an upper entrance, thereby arranging a metal wiring without overhang on the semiconductor device. CONSTITUTION: An insulating layer is arranged on a semiconductor substrate(100). A trench of a predetermined pattern or a via hole(110) are arranged on the insulating layer. The upper part or entrance of the trench or via hole arranged on the semiconductor substrate is processed with an adsorption suppressing gas including hydrogen using an ion injection method. A conductive material is evaporated in the trench or via hole arranged on the semiconductor substrate.

Abstract translation: 目的：提供一种通过离子注入法的半导体器件的布线形成方法，用于使导电层从沟槽的底部均匀蒸发到上部入口，从而在半导体器件上布置没有悬垂的金属布线。 构成：在半导体衬底（100）上布置绝缘层。 在绝缘层上布置有预定图案的沟槽或通孔（110）。 通过使用离子注入法对配置在半导体基板上的沟槽或通孔的上部或入口进行包括氢的吸附抑制气体的处理。 导电材料在布置在半导体衬底上的沟槽或通孔中蒸发。

公开(公告)号：KR101069630B1

公开(公告)日：2011-10-05

申请号：KR1020080039447

申请日：2008-04-28

Applicant: 성균관대학교산학협력단

Inventor： 이내응 ,  문학기 ,  김선일

IPC: H01L21/28

Abstract: 본발명은흡착억제제를이용한반도체소자의금속배선형성방법에관한것으로, 본발명에따른반도체소자의금속배선형성방법은, 하부구조가형성된반도체기판상에절연층을형성하고, 상기절연층상에일정패턴의트렌치(trench) 또는비아(via)홀을형성하는단계와; 상기트렌치또는비아홀이형성된반도체기판상에, 상기도전물질의증착을위한증착공정과상기도전물질의흡착을억제하기위한흡착억제공정을, 상기트렌치또는비아홀이상기도전물질로채워질때까지연속적, 단계적, 순환적방법중에서선택된적어도어느하나의방법으로수행하여도전층을형성하는단계와; 상기절연층의상부가노출될때까지상기도전층제거공정을수행하여상기트렌치또는비아홀을제외한부분의도전층을제거함에의해금속배선을형성하는단계를구비한다. 본발명에따르면, 금속배선형성시보이드나연결선없는균일한증착이가능한장점이있다.

公开(公告)号：KR1020090113633A

公开(公告)日：2009-11-02

申请号：KR1020080039447

申请日：2008-04-28

Applicant: 성균관대학교산학협력단

Inventor： 이내응 ,  문학기 ,  김선일

IPC: H01L21/28

CPC classification number: H01L21/76877 ,  H01L21/28556 ,  H01L21/3212 ,  H01L21/76846

Abstract: PURPOSE: A method for fabricating metal line using adsorption inhibitor in semiconductor device is provided to secure the reliability of the metal wiring and semiconductor device. CONSTITUTION: The insulating layer(110) is formed on the semiconductor substrate(100). The trench or the via hall of the constant pattern is formed on the insulating layer. The deposition process for the conducting material is performed. The adsorption suppression process for restraining the adsorption of the conducting material is performed. The process of removing the conductive layer is performed to expose the insulating layer. The metal wiring(150c) is formed by removing the conductive layer.

Abstract translation: 目的：提供一种在半导体器件中使用吸附抑制剂制造金属线的方法，以确保金属布线和半导体器件的可靠性。 构成：绝缘层（110）形成在半导体衬底（100）上。 在绝缘层上形成恒定图案的沟槽或通孔室。 执行导电材料的沉积工艺。 执行用于抑制导电材料的吸附的吸附抑制过程。 执行去除导电层的过程以暴露绝缘层。 通过去除导电层来形成金属布线（150c）。