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公开(公告)号：KR1020170108675A
公开(公告)日：2017-09-27
申请号：KR1020160032952
申请日：2016-03-18
Applicant: 연세대학교 산학협력단
Abstract: 일실시예에따른에너지하베스팅용직류-직류변환장치는연결부하로흐르는전류값에기초하여헤비(heavy) 모드또는라이트(light) 모드를결정하는결정부, 상기결정된모드에기초하여, 열전소자어레이의구성을직렬또는병렬로재구성하는어레이재구성부, 상기결정된모드에기초하여, 변환부의스위칭주파수를제어하는주파수제어부및 상기제어된스위칭주파수에기초하여, 상기재구성된열전소자어레이에서생성된직류전압을상기부하에필요한전압으로변환하는변환부를포함한다.
Abstract translation: 根据实施例的用于能量收集的DC-DC转换设备包括：确定单元，其基于流入连接的负载的电流的值来确定重模式或轻模式;以及确定单元，其基于所确定的模式， 频率控制单元，用于基于所确定的模式来控制转换单元的开关频率;以及控制单元，用于基于受控的开关频率来控制重新配置的热元件阵列中产生的DC电压， 达到负载所需的电压。
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公开(公告)号：KR101742760B1
公开(公告)日：2017-06-02
申请号：KR1020150175941
申请日：2015-12-10
Applicant: 연세대학교 산학협력단
CPC classification number: H02M3/158 , H02M2003/1566
Abstract: 본발명은저면적으로구현가능하면서도높은효율을나타내는직류-직류변환기를제공한다. 본발명의일 실시예에따른직류-직류변환기는, 입력전압을공급하는전력공급부; 출력전압이출력되는출력단과상기전력공급부사이에연결된인덕터; 상기인덕터의양단에연결되어피드백전압을생성하는에뮬레이터(emulator); 및상기출력전압과상기피드백전압을기반으로, 시간영역(time domain) 제어를통해상기전력공급부를제어하는제어회로를포함할수 있다.
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公开(公告)号：KR101621855B1
公开(公告)日：2016-05-19
申请号：KR1020140043045
申请日：2014-04-10
Applicant: 연세대학교 산학협력단
Abstract: 본발명은전하펌프및 위상동기루프에관한것으로, 본발명의실시예에따른전하펌프는, 제1 게이트에풀업(pull-up) 신호가인가되는제1 스위칭트랜지스터; 제2 게이트에풀다운(pull-down) 신호가인가되는제2 스위칭트랜지스터; 제1 전류미러를통해제1 스위칭트랜지스터에풀업전류를형성하는제1 전류소스트랜지스터; 및제2 전류미러를통해제2 스위칭트랜지스터에풀다운전류를형성하는제2 전류소스트랜지스터를포함하고, 제1 전류소스트랜지스터및 제2 전류소스트랜지스터의바디(body)에, 제1 스위칭트랜지스터와제2 스위칭트랜지스터의드레인또는소스사이에형성되는제어전압이인가된다.
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公开(公告)号：KR1020150121291A
公开(公告)日：2015-10-29
申请号：KR1020140046184
申请日：2014-04-17
Applicant: 연세대학교 산학협력단
CPC classification number: G04F10/005 , H03L7/0891 , H03L7/0895 , H03M1/00 , H03M1/12 , H03M1/1225 , H03M2201/4233
Abstract: 본발명은시간디지털변환기에관한것으로, 시간디지털변환기는, 순환구조로연결되고인에이블(enable) 신호에따라동작하는복수의제1 지연셀을포함하는제1 게이티드링오실레이터(gated ring oscillator); 순환구조로연결되고인에이블신호에따라동작하는복수의제2 지연셀을포함하는제2 게이티드링오실레이터; 제1 게이티드링오실레이터에서순환하는제1 순환신호에대해소정의위상차를갖도록, 제2 게이티드링오실레이터에서순환하는제2 순환신호의위상을조절하는위상조절부; 및복수의제1 지연셀 및복수의제2 지연셀의출력신호들을샘플링하여인에이블신호의지속시간에대응하는디지털값을출력하는디지털변환부를포함한다.
Abstract translation: 时间数字转换器技术领域本发明涉及时间数字转换器。 时间数字转换器包括：第一选通环形振荡器，其包括以循环结构连接并根据使能信号操作的多个第一延迟单元; 第二选通环形振荡器，其包括以循环结构连接并根据使能信号操作的多个第二延迟单元; 相位调整部，其调节在所述第二选通环形振荡器中循环的第二循环信号的相位，以与在所述第一选通环形振荡器中循环的所述第一循环信号具有一定的相位差; 以及数字转换部件，其通过对多个第一延迟单元和多个第二延迟单元的输出信号进行采样来响应于使能信号的持续时间输出数字值。
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公开(公告)号：KR101477053B1
公开(公告)日：2014-12-31
申请号：KR1020140019135
申请日：2014-02-19
Applicant: 연세대학교 산학협력단
CPC classification number: G04F10/005 , H03K5/135 , H03L7/085 , H03L2207/50
Abstract: The present invention relates to a time-digital converter and a phase-locked loop circuit using the same.The time-digital converter according to an embodiment of the present invention includes: a first stage of delaying a start signal by a first delay time to compare a stop signal with the delayed start signal or delaying the stop signal by a second delay time to compare the delayed stop signal with the delayed start signal; a second stage of delaying the start signal output from the first stage by a third delay time to compare the stop signal output from the first stage with the third delayed start signal or delaying the stop signal output from the first stage by a forth delay time to compare the fourth delayed stop signal with the third delayed start signal; and a controller which circularly inputs the start signal and the stop signal output from the second stage a preset number of times, and changes the first to fourth delay times every circle.
Abstract translation: 本发明涉及一种时数数字转换器和使用该数字转换器的锁相环电路。根据本发明实施例的时数转换器包括：将起始信号延迟第一延迟时间的第一级， 将停止信号与延迟的起始信号进行比较，或将停止信号延迟第二延迟时间，以将延迟的停止信号与延迟的起始信号进行比较; 将从第一级输出的起始信号延迟第三延迟时间的第二级，以将从第一级输出的停止信号与第三延迟开始信号进行比较，或将从第一级输出的停止信号延迟第四延迟时间， 将第四延迟停止信号与第三延迟启动信号进行比较; 以及将从第二级输出的开始信号和停止信号循环输入预定次数的控制器，并且每循环改变第一至第四延迟时间。
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Patent Agency Ranking
公开(公告)号：KR101418045B1
公开(公告)日：2014-07-14
申请号：KR1020130006034
申请日：2013-01-18
Applicant: 연세대학교 산학협력단
Abstract: The present invention relates to a temperature detection circuit and a temperature detection method. The temperature detection circuit comprises: a delay part delaying an input clock signal to generate a feedback clock signal, and having logic gates for varying a delay time by temperatures; a delay control part comparing the feedback clock signal with a reference clock signal, and controlling the logic gates of the delay part according to the compared results; and an input signal control part for selecting one input clock signal among the feedback clock signal and the reference clock signal based on the circulation cycle number of the input clock signal, and inputting the selected input clock signal in the delay part.
Abstract translation: 本发明涉及温度检测电路和温度检测方法。 温度检测电路包括：延迟部，延迟输入时钟信号以产生反馈时钟信号，并具有用于根据温度改变延迟时间的逻辑门; 延迟控制部分，将反馈时钟信号与参考时钟信号进行比较，并根据比较结果控制延迟部分的逻辑门; 以及输入信号控制部分，用于基于输入时钟信号的循环周期数，在反馈时钟信号和参考时钟信号中选择一个输入时钟信号，并在延迟部分中输入所选择的输入时钟信号。
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公开(公告)号：KR101323372B1
公开(公告)日：2013-10-30
申请号：KR1020110094365
申请日：2011-09-20
Applicant: 연세대학교 산학협력단
IPC: G01R31/28
Abstract: 본 발명의 일 실시예에 따른 신호 발생 장치는 기준 신호, 엣지 버니어와 정수 지연 생성기의 동작 제어신호 및 상기 엣지 버니어의 처리 신호를 입력받아, 상기 기준 신호를 소정 간격 지연시킨 출력 신호를 생성하는 오프셋 보정부를 포함한다.
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公开(公告)号：KR1020120086036A
公开(公告)日：2012-08-02
申请号：KR1020110007237
申请日：2011-01-25
Applicant: 에스케이하이닉스 주식회사 , 연세대학교 산학협력단
IPC: G05F1/567
CPC classification number: G01K7/346
Abstract: PURPOSE: A temperature sensing circuit is provided to reduce the area thereof while maintaining temperature sensing resolution by extending the pulse width of a source signal to generate a comparison signal and using a fine delay unit. CONSTITUTION: A signal generating unit(210) includes a delay line and generates a source signal having a pulse width corresponding to the delay value of the delay line. A pulse width extension unit(220) extends the pulse width of the source signal to generate a comparison signal. A change sensing unit(230) detects temperature changes using the pulse width difference between the comparison signal and a reference signal.
Abstract translation: 目的：提供一种温度检测电路，通过扩展源信号的脉冲宽度，同时保持温度感测分辨率，以产生比较信号并使用精细延迟单元来减小其面积。 构成：信号生成单元（210）包括延迟线，并产生具有对应于延迟线的延迟值的脉冲宽度的源极信号。 脉冲宽度扩展单元（220）扩展源信号的脉冲宽度以产生比较信号。 改变感测单元（230）使用比较信号和参考信号之间的脉冲宽度差来检测温度变化。
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公开(公告)号：KR1020110078355A
公开(公告)日：2011-07-07
申请号：KR1020090135143
申请日：2009-12-31
Applicant: 연세대학교 산학협력단
IPC: G11C8/00 , G11C11/407 , G11C7/10 , G11C8/10
CPC classification number: G11C7/22 , G11C11/4076 , H03K5/13 , H03L7/0812 , H03L7/089
Abstract: PURPOSE: A phase detecting device is provided to obtain a wide phase sensing range regardless of a duty cycle by using an analog phase detector. CONSTITUTION: A phase detecting device(110) comprises an analog phase detecting unit(111), a latch circuit(112), and a decoder(113). The latch circuit is connected to the analog phase detector and retains data from the analog phase detecting unit. The decoder decodes data from the latch circuit. The analog phase detecting unit receives a first clock signal and a second clock signal and generates a third clock synchronized with the rising edge of a first clock signal and a fourth clock signal synchronized with the rising edge of the second clock signal.
Abstract translation: 目的：通过使用模拟相位检测器，提供相位检测装置以获得宽的相位感测范围，而不管占空比。 构成：相位检测装置（110）包括模拟相位检测单元（111），锁存电路（112）和解码器（113）。 锁存电路连接到模拟相位检测器，并保留来自模拟相位检测单元的数据。 解码器解码来自锁存电路的数据。 模拟相位检测单元接收第一时钟信号和第二时钟信号，并产生与第二时钟信号的上升沿同步的第一时钟信号和第四时钟信号的上升沿同步的第三时钟。
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公开(公告)号：KR101027759B1
公开(公告)日：2011-04-07
申请号：KR1020090129082
申请日：2009-12-22
Applicant: 연세대학교 산학협력단
IPC: G11C8/00
CPC classification number: G11C7/222 , G11C11/4076 , H03K5/1565 , H03K19/096 , H03L7/0812 , H03L7/085
Abstract: PURPOSE: A delayed locked loop and a duty cycle correction circuit thereof are provided to being implemented in a narrow area while having high resistance against a process and the change of a voltage and temperature. CONSTITUTION: In a delayed locked loop and a duty cycle correction circuit thereof, a delay unit outputs a second clock signal. The second clock signal is delayed more than a first clock signal. A first divider(220) generates a third clock signal. The third clock signal has a frequency lower than the first clock signal. A second divider(230) generates a fourth clock signal. The fourth clock signal has the frequency lower than the second clock signal. Phase detectors(110,240) generate a control signal. A combining unit(260) merges first and the second clock signals and generates an output clock signal.
Abstract translation: 目的：提供一种延迟锁定环及其占空比校正电路，以实现在较窄的区域，同时具有高的电阻和电压和温度的变化。 构成：在延迟锁定环及其占空比校正电路中，延迟单元输出第二时钟信号。 第二时钟信号被延迟多于第一时钟信号。 第一分频器（220）产生第三时钟信号。 第三时钟信号的频率低于第一时钟信号。 第二分频器（230）产生第四时钟信号。 第四时钟信号具有低于第二时钟信号的频率。 相位检测器（110,240）产生控制信号。 组合单元（260）首先合并第二时钟信号并产生输出时钟信号。
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