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公开(公告)号：KR1019970004430B1
公开(公告)日：1997-03-27
申请号：KR1019930028269
申请日：1993-12-17
IPC: H01L21/331 , H01L29/73
Abstract: A method of fabricating a bipolar transistor using selective growth includes the first step of forming a highly doped sub-collector 1 on a silicon substrate, forming a collector thin film 2 thereon and heat-treating a collector region 5, the second steps of forming a base thin film 6 and emitter thin film 7 on the substrate, sequentially forming a buffer insulating layer 8 and oxidation blocking insulating layer 7, and sequentially etching the insulating layers 8 and 9 and emitter thin film 7 to leave the base thin film 6, the third step of forming a side insulating layer 10 on both sides of the emitter thin film 7, selectively forming a thin film 11 for the base electrode on the exposed base thin film 6 and forming a photoresist pattern 12 for defining the base electrode, the fourth step of removing a portion other than a thin film 13 for the base electrode and base thin film 14 using the photoresist pattern 12 as a mask, the fifth step of removing the photoresist pattern 12, selectively oxidizing the thin film 13 for the base electrode to form oxide layers 15 and 16, diffusing impurities from the emitter thin film 7 and thin film 17 for the base electrode through heat treatment to form an emitter-base junction 19 and nonactive base region 18, and the sixth step of selectively removing the oxidation blocking insulating layer 9 by self-alignment, removing the buffer insulating layer 8 and forming a metal thin film 20 on the base thin film 17 and collector 21.
Abstract translation: 使用选择性生长制造双极晶体管的方法包括在硅衬底上形成高掺杂子集电极1的第一步骤，在其上形成集电极薄膜2并热处理集电极区域5，第二步骤形成 基底薄膜6和发射极薄膜7，依次形成缓冲绝缘层8和氧化阻挡绝缘层7，并依次蚀刻绝缘层8,9和发射极薄膜7以离开基底薄膜6， 在发射极薄膜7的两侧形成侧绝缘层10的第三步骤，在露出的基底薄膜6上选择性地形成用于基底电极的薄膜11，并形成用于限定基极的光刻胶图案12，第四步骤 使用光致抗蚀剂图案12作为掩模去除除了用于基底电极和基底薄膜14的薄膜13之外的部分的步骤，除去光致抗蚀剂图案12的第五步骤 对基极的薄膜13进行氧化以形成氧化物层15和16，通过热处理从发射极薄膜7和基极薄膜17扩散杂质，以形成发射极 - 基极结19和非活性碱性区18 以及通过自对准选择性去除氧化阻挡绝缘层9的第六步骤，去除缓冲绝缘层8并在基底薄膜17和集电体21上形成金属薄膜20。
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公开(公告)号：KR1019960016826B1
公开(公告)日：1996-12-21
申请号：KR1019930026790
申请日：1993-12-08
IPC: H01L21/302
Abstract: forming a silicon substrate(10) where structures with different pattern sizes are formed; depositing a CVD SiO2 film(12) after depositing a polysilicon film(11) on the silicon substrate(10); leaving the CVD SiO2 film(12) on the bottom and side wall by polishing the CVD SiO2 film(12) revealed on top of a trench pattern; etching the revealed polysilicon film(11) to leave the polysilicon film and the CVD SiO2 film on the trench side wall; and planarizing the etched polysilicon film by mechanical and chemical polishing method after forming a polysilicon spike(13).
Abstract translation: 形成其中形成具有不同图案尺寸的结构的硅衬底（10） 在硅衬底（10）上沉积多晶硅膜（11）之后沉积CVD SiO 2膜（12）; 通过抛光在沟槽图案顶部上显示的CVD SiO 2膜（12），将CVD SiO 2膜（12）留在底壁和侧壁上; 蚀刻显露的多晶硅膜（11），以留下沟槽侧壁上的多晶硅膜和CVD SiO 2膜; 以及在形成多晶硅尖峰（13）之后通过机械和化学抛光方法平坦化蚀刻的多晶硅膜。
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公开(公告)号：KR1019960014447B1
公开(公告)日：1996-10-15
申请号：KR1019930026303
申请日：1993-12-03
IPC: H01L21/76
Abstract: (A) removing a LPCVD oxide film(5), a nitrided film(4) and an oxide film(3) on a region(6); (B) forming a trench by etching a substrate on the region(6) selectively, and forming a first oxide film(8) on the trench; (C) forming a mask oxide film(10) by etching the LPCVD oxide film(5); (D) forming a second oxide film(11); (E) removing the second oxide film(11) on the bottom(12) of the trench and the exposed nitrided film(4) of a region(14); (F) grounding the substrate by forming p+ region(16) after filling the trench with Boron-doped polysilicone(15); (G) obtaining a wafer surface(17) of flattening polysilicone by etching the oxide film(13) on the nitrided film(4); (H) defining an active region by using a photoresist film(18); (I) forming an thermal oxide film(20) by etching the exposed nitrided film(4).
Abstract translation: （A）在区域（6）上去除LPCVD氧化膜（5），氮化膜（4）和氧化膜（3）; （B）选择性地蚀刻所述区域（6）上的衬底形成沟槽，以及在所述沟槽上形成第一氧化膜（8）; （C）通过蚀刻LPCVD氧化膜（5）形成掩模氧化膜（10）; （D）形成第二氧化膜（11）; （E）去除所述沟槽的底部（12）上的所述第二氧化物膜（11）和所述暴露的区域（14）的氮化膜（4）; （F）通过在硼掺杂多硅氧烷（15）填充沟槽之后形成p +区域（16）使衬底接地; （G）通过蚀刻氮化膜（4）上的氧化膜（13）来获得平坦化的聚硅氧烷的晶片表面（17）; （H）通过使用光致抗蚀剂膜（18）限定有源区域; （I）通过蚀刻暴露的氮化膜（4）形成热氧化膜（20）。
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公开(公告)号：KR1019960026763A
公开(公告)日：1996-07-22
申请号：KR1019940034160
申请日：1994-12-14
IPC: H01L27/082
Abstract: 본 발명은 컴퓨터나 광통신 등의 고속 정보처리 시스템에 유용한 고집적형 자기정렬 바이폴라 트랜지스터를 제조하는 방법에 관한 것이다.
본 발명에서는 소자격리를 위한 트렌치 격리공정을 개선하여 소자의 집적도를 향상시키고, 활성영역외의 컬렉터 영역을 모두 저심도랑과 유사한 깊이를 갖도록 열산화함으로써 도랑의 수를 감소시켜 공정을 단순화한다.
또한, 배선전극과 기판과의 기생용량과 관계있는 절연막의 두께를 저심도랑의 두께만큼 임의로 조절하여 금속배선의 기생용량을 줄인다. 가급적 SEG 공정을 배제하여 공정을 단순화시킴과 아울러 에미터, 베이스 및 컬렉터를 모두 자기정렬시킨다.-
Patent Agency Ranking
公开(公告)号：KR1019960026425A
公开(公告)日：1996-07-22
申请号：KR1019940035491
申请日：1994-12-21
IPC: H01L21/331
Abstract: 본 발명에서는, 쌍극자 트랜지스터의 컬렉터 접합층에 금속성 박막의 컬렉터 메몰층을 증착시킨 후 소자격리영역을 식각하여 외부컬렉터 저항을 최소화하고, 절연막과 다결정막을 증착하여 기판에 직접 접합시키고 반대편의 기판을 기계화 연마로 평탄화시킨다.
이로써, 컬렉터 접합층의 전류와 같은 방향의 측면저항이 금속성 컬렉터 메몰층에 의해 거의 없어지므로 고속 및 고주파특성 등의 트랜지스터 성능향상을 얻을 수 있다.-
公开(公告)号：KR1019960019595A
公开(公告)日：1996-06-17
申请号：KR1019940032108
申请日：1994-11-30
IPC: H01L21/328
Abstract: 본 발명은 베이스 저항을 줄이고 컬렉터-베이스 간의 접합용량을 감소시켜 소자의 성능을 향상시킬 수 있는 쌍극자 트랜지스터의 제조방법을 제공하는데 목적이 있는 것으로, 산화막을 이용한 소자격리 공정과, 켈렉터 영역에 산화막을 성장시키는 공정과, 베이스 박막/얇은 산화막/티타늄 박막/산화막을 순차적으로 적층하는 공정과, 감광막을 마스크로서 사용하여 고농도의 붕소를 이온주입하고 식각 속도 차이를 이용하여 에미터 영역의 산화막을 식각하고 노출된 티타늄 박막을 선택적으로 식각하고 열처리하여 티타늄 실리사이드를 형성하는 공정과, 베이스 전극인 티타늄 실리사이드 박막의 측면에 측면 산화막을 형성하여 베이스와 에미터를 결리시키는 공정과, 에미터 전극용 실리콘 박막의 형성 및 열처리에 의해 에미터를 형성하는 공정 및, 접점과 금속배선 형성 공정을 포함한다.
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公开(公告)号：KR1019940007656B1
公开(公告)日：1994-08-22
申请号：KR1019910024508
申请日：1991-12-26
IPC: H01L29/73
Abstract: The method is for manufacturing a heterojunction and homojunction dipole transistor using a substrate connection method. The method includes the steps of: (A) forming silicon layers (31,32) on a P-type substrate (30); (B) etching the silicon layer to form device region and forming an insulating layer (33); (C) spraying polycrystal silicon (3) and connecting to another P-type silicon substrate (35); (D) polishing the silicon layer (31) until an insulating layer (33) is exposed; (E) forming connecting area (36) on a silicon layer (32) and forming an insulating layer (37), a polycrystal silicon layer (38), and a silicon layer (39); (F) etching to form an active region and forming a groove on side wall of an insulating layer (37); and (G) spraying polycrystal silicon and heating to form an oxide layer.
Abstract translation: 该方法是使用基板连接方法制造异质结和同质结偶极晶体管。 该方法包括以下步骤：（A）在P型衬底（30）上形成硅层（31,32）; （B）蚀刻硅层以形成器件区域并形成绝缘层（33）; （C）喷射多晶硅（3）并连接到另一个P型硅衬底（35）; （D）研磨硅层（31）直到暴露绝缘层（33）; （E）在硅层（32）上形成连接区域（36）并形成绝缘层（37），多晶硅层（38）和硅层（39）; （F）蚀刻以形成有源区并在绝缘层（37）的侧壁上形成凹槽; 和（G）喷涂多晶硅并加热形成氧化物层。
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公开(公告)号：KR100299665B1
公开(公告)日：2001-11-22
申请号：KR1019970069556
申请日：1997-12-17
Applicant: 한국전자통신연구원
IPC: H01L29/737
Abstract: PURPOSE: A method for forming an ohmic contact layer of a hetero-junction bipolar transistor is provided to improve efficiency of a fabricating process and reduce a fabricating cost by forming simultaneously ohmic electrodes on an emitter, a base, and a collector. CONSTITUTION: A buffer layer, a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer are grown on a compound semiconductor substrate. A surface of the base layer is exposed by etching the emitter cap layer and the emitter layer. A surface of the sub-collector layer is exposed by patterning the base layer and the collector layer. An ohmic electrode is formed simultaneously on an emitter region, a base region, and a collector region. A Ti metal layer(8), a Ti nitride metal layer, a compositionally graded tungsten nitride metal layer, and a tungsten metal layer are deposited sequentially on the substrate. A titanium metal layer(8) and a platinum metal layer are formed thereon. An n type emitter and an n type collector ohmic electrode and a p type base ohmic electrode are formed simultaneously by performing an etch process. An isolation region is formed by performing a mesa etch process. A dielectric insulating layer(17) is applied on a whole surface of the above structure. A metal line including the titanium layer and an aurum layer(18) is formed by performing selectively the etch process.
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