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公开(公告)号：KR1019930007326B1
公开(公告)日：1993-08-05
申请号：KR1019900021824
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F5/00
Abstract: The circuit comprises the first barrel shifter (1) which obtains original signal data and outputs shifted data according to the offset signal, the 2nd barrel shifter (2) which obtains the above shifted data and outputs SIGN data shifted by the inverting signal of a bit width designating signal, the decoder (4) to decode the above signal.
Abstract translation: 该电路包括获得原始信号数据并根据偏移信号输出移位数据的第一桶形移位器（1），获得上述移位数据的第二桶形移位器（2），并输出通过位的反相信号移位的SIGN数据 宽度指定信号，解码器（4）解码上述信号。
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Patent Agency Ranking
公开(公告)号：KR1019930007014B1
公开(公告)日：1993-07-26
申请号：KR1019900021834
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F9/34
Abstract: The circuit for processing standby state includes a latch (1) for latching address signal of a processor at low state of processor output signal (CLK) and for sending latched signal to a flip-flop (2) and a multiplexer latch (4), a flip-flop (2) for delaying processor internal address (ADDR) signal by one clock and for outputting the delayed signal to a scan flip-flop (3) a scan flip-flop (3) for selecting input terminals (T1,D) according to state of stand-by signal (IDWAIT), and a multiplexer latch (4) for selecting signal between output signal of the latch and the scan flip-flop accoding to state of stand-by signal (IDWAIT) and for outputting the selected signal to valid address line (I-EA).
Abstract translation: 用于处理待机状态的电路包括用于在处理器输出信号（CLK）的低状态下锁存处理器的地址信号并将锁存信号发送到触发器（2）和多路复用器锁存器（4）的锁存器（1） 用于将处理器内部地址（ADDR）信号延迟一个时钟并将延迟的信号输出到扫描触发器（3）的触发器（2），用于选择输入端子（T1，D）的扫描触发器 ），以及多路复用器锁存器（4），用于选择锁存器的输出信号和根据待机信号状态（IDWAIT）的扫描触发器之间的信号，并且用于输出所述待机信号 选择信号到有效地址线（I-EA）。
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