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Patent Agency Ranking
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公开(公告)号：KR1019930007043B1
公开(公告)日：1993-07-26
申请号：KR1019900021835
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F9/34
Abstract: The circuit is for generating always constant "0" through 3 independent read terminals by designating constant "0" to a certain register to remove the inconvenience when using register. It includes 6 NOR gates (N1-N6), 9 inverters (I1-I9) through which the address signal of terminal A reading (RD-A), the address signal of terminal B reading (RD-B) and the address signal of terminal C reading (RD-C) are passed.
Abstract translation: 该电路用于通过3个独立的读取端子始终保持恒定的“0”，通过向某个寄存器指定常量“0”，以消除使用寄存器时的不便。 它包括6个或非门（N1-N6），9个反相器（I1-I9），通过该逆变器输出端子A读取地址信号（RD-A），端子B读取地址信号（RD-B）和地址信号 终端C读取（RD-C）通过。
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公开(公告)号：KR1019930007012B1
公开(公告)日：1993-07-26
申请号：KR1019900021839
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F9/22
Abstract: The circuit is for clearing or setting the bit field variably appointed to improve the operational ability of graphic processing program. It includes a decoder (1) for processing the bit width appointing signal to be outputted as 32 bit signal which has "1"s as many as the size of bit, a barrel shifter (2) for shifting the output of the decoder (1) by the offset and signal from the input terminals (S16,S8,S6,S4,S2,S1), and a multiplexer (3) composed of an IC (4) for generating data output set or cleard by the bit width offset.
Abstract translation: 该电路用于清除或设置可变指定的位域，以提高图形处理程序的操作能力。 它包括一个解码器（1），用于处理要输出的比特宽度指定信号作为比特大小为“1”的32比特信号，用于移位解码器（1）的输出的桶形移位器（2） ）和来自输入端子（S16，S8，S6，S4，S2，S1）的偏移和信号，以及由用于产生数据输出集合或通过位宽度偏移而消除的IC（4）组成的多路复用器（3）。
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公开(公告)号：KR1019930001920B1
公开(公告)日：1993-03-20
申请号：KR1019900021829
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: G06F7/38
Abstract: The circuit provides the lowest cost of production. Among the input data of 32 bit, a lower rank 8 bit (0-7), a middle 8 bit and a higher rank 8 bit are inputted to the input terminal of the first, the second, and the third zero (0) detecting circuit, respectively. Each 4 bit of input data is inputted to the input terminal of adding circuit (4). The carry error inputted from outer is applied to the carry input terminal of adding circuit directly. The output of NAND gate inputted from the first zero detecting circuit is applied to the carry input terminal of adding circuit (6). The output inputted from the second, the first zero detecting circuit is applied to the carry input terminal of adding circuit (8).
Abstract translation: 该电路提供最低的生产成本。 在32位的输入数据中，低位8位（0-7），中间8位和高8位输入到第一，第二和第三零（0）检测的输入端 电路。 每4位输入数据被输入到加法电路（4）的输入端。 从外部输入的进位误差直接加到加法电路的进位输入端。 从第一零检测电路输入的与非门的输出被加到加法电路（6）的进位输入端。 从第二输入的输出，第一零检测电路被施加到加法电路（8）的进位输入端。
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