公开(公告)号：WO2005034225A1

公开(公告)日：2005-04-14

申请号：PCT/US2004/031037

申请日：2004-09-17

Applicant: ADVANCED MICRO DEVICES, INC. ,  KAMMLER, Thorsten ,  WIECZOREK, Karsten ,  FRENKEL, Austin

Inventor： KAMMLER, Thorsten ,  WIECZOREK, Karsten ,  FRENKEL, Austin

IPC: H01L21/285

CPC classification number: H01L21/28518 ,  H01L21/28052 ,  H01L29/665

Abstract: By forming a buried nickel silicide layer (260A) followed by a cobalt silicide layer (261A) in silicon containing regions, such as a gate electrode of a field effect transistor, the superior characteristics of both silicides may be combined so as to provide the potential for further device scaling without unduly compromising the sheet resistance and the contact resistance of scaled silicon circuit features.

Abstract translation: 通过在含硅区域（例如场效应晶体管的栅电极）中形成掩埋的硅化镍层（260A），随后是硅化钴层（261A），可以组合两种硅化物的优异特性以提供电位 用于进一步的器件定标，而不会不适当地损害比例硅电路特征的薄层电阻和接触电阻。

公开(公告)号：WO2008094699A1

公开(公告)日：2008-08-07

申请号：PCT/US2008/001408

申请日：2008-01-31

Applicant: ADVANCED MICRO DEVICES, INC. ,  WEI, Andy ,  KAMMLER, Thorsten ,  BOSCHKE, Roman ,  HORSTMANN, Manfred

Inventor： WEI, Andy ,  KAMMLER, Thorsten ,  BOSCHKE, Roman ,  HORSTMANN, Manfred

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L29/66636 ,  H01L21/76256 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/78684 ,  Y10S438/938

Abstract: By combining a respectively adapted lattice mismatch between a first semiconductor material (4, 104) in a channel region (112) and an embedded second semiconductor material (9, 109) in an source/drain region (110) of a transistor, the strain transfer into the channel region (112) is increased. The lattice mismatch may be adapted by a biaxial strain in the first semiconductor material (4, 104). The lattice mismatch may be adjusted by a biaxial strain in the first semiconductor material (4, 104). In particular, the strain transfer of strain sources including the embedded second semiconductor material (9, 109) as well as a strained overlayer is increased. According to one illustrative embodiment, regions of different biaxial strain may be provided for different transistor types.

Abstract translation: 通过在沟道区域（112）中的第一半导体材料（4,104）和晶体管的源极/漏极区域（110）中嵌入的第二半导体材料（9,109）之间的分别适配的晶格失配相结合， 传送到信道区域（112）的数量增加。 晶格失配可以通过第一半导体材料（4,104）中的双轴应变来适应。 可以通过第一半导体材料（4,104）中的双轴应变来调整晶格失配。 特别地，包括嵌入的第二半导体材料（9,109）以及应变覆盖层的应变源的应变传递增加。 根据一个说明性实施例，可以为不同的晶体管类型提供不同双轴应变的区域。

公开(公告)号：WO2007130241A1

公开(公告)日：2007-11-15

申请号：PCT/US2007/007844

申请日：2007-03-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  WEI, Andy ,  KAMMLER, Thorsten ,  HOENTSCHEL, Jan ,  HORSTMANN, Manfred

Inventor： WEI, Andy ,  KAMMLER, Thorsten ,  HOENTSCHEL, Jan ,  HORSTMANN, Manfred

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/762 ,  H01L21/84 ,  H01L29/786

CPC classification number: H01L29/78612 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/1045 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78621 ,  H01L29/78684

Abstract: By forming a portion (209A, 309A, 409A) of a PN junction (209, 309, 409) within strained silicon/germanium material (207, 307, 407) in SOI transistors (200, 300, 400) with a floating body (221, 321) architecture, the junction leakage may be significantly increased, thereby reducing floating body effects. The positioning of a portion (209A, 309A, 409A) of the PN junction (209, 309, 409) within the strained silicon/germanium material (207, 307, 407) may be accomplished on the basis of implantation and anneal techniques, contrary to conventional approaches in which in situ doped silicon/germanium is epitaxially grown so as to form the deep drain and source regions. Consequently, high drive current capability may be combined with a reduction of floating body effects.

Abstract translation: 通过在具有浮体的SOI晶体管（200,300,400）中形成应变硅/锗材料（207,307,407）内的PN结（209,309,409）的部分（209A，309A，409A） 221，321）架构，结点泄漏可能会显着增加，从而减少浮体的影响。 PN结（209,309,409）在应变硅/锗材料（207,307,407）内的部分（209A，309A，409A）的定位可以基于注入和退火技术来实现，相反 涉及原位掺杂硅/锗外延生长以形成深漏极和源极区的常规方法。 因此，高驱动电流能力可以与减少浮体效应相结合。

公开(公告)号：WO2007126495A1

公开(公告)日：2007-11-08

申请号：PCT/US2007/004689

申请日：2007-02-21

Applicant: ADVANCED MICRO DEVICES, INC. ,  WEI, Andy ,  KAMMLER, Thorsten ,  HOENTSCHEL, Jan ,  HORSTMANN, Manfred ,  JAVORKA, Peter ,  BLOOMQUIST, Joe

Inventor： WEI, Andy ,  KAMMLER, Thorsten ,  HOENTSCHEL, Jan ,  HORSTMANN, Manfred ,  JAVORKA, Peter ,  BLOOMQUIST, Joe

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/665 ,  H01L21/7624 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

Abstract: By recessing (112D, 212D) drain and source regions (114, 214), a highly stressed layer (118, 218), such as a contact etch stop layer, may be formed in the recess (112, 212) in order to enhance the strain generation in the adjacent channel region (104, 204) of a field effect transistor (100, 200). Moreover, a strained semiconductor material (230) may be positioned in close proximity to the channel region (104, 204) by reducing or avoiding undue relaxation effects of metal suicides (217), thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain- inducing mechanism.

Abstract translation: 通过凹陷（112D，212D）漏极和源极区域（114,214），可以在凹部（112,212）中形成高应力层（118,218），例如接触蚀刻停止层，以便增强 在场效应晶体管（100,200）的相邻沟道区（104,204）中产生应变。 此外，应变半导体材料（230）可以通过减少或避免金属硅化物（217）的不适当的松弛效应来定位在通道区域（104,204）附近，从而也为应变产生提供更高的效率。 在一些方面，两种效应可以组合以获得更有效的应变诱导机制。

公开(公告)号：WO2007027473A3

公开(公告)日：2007-03-08

申请号：PCT/US2006/032743

申请日：2006-08-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  HOENTSCHEL, Jan ,  WEI, Andy ,  KAMMLER, Thorsten ,  RAAB, Michael

Inventor： HOENTSCHEL, Jan ,  WEI, Andy ,  KAMMLER, Thorsten ,  RAAB, Michael

IPC: H01L21/8238 ,  H01L21/265 ,  H01L27/092

Abstract: By forming a strained semiconductor layer (117, 217) in a PMOS transistor (110, 210), a corresponding compressively strained channel region (11 IA) may be achieved, while, on the other hand, a corresponding strain in the NMOS transistor (120, 220) may be relaxed. Due to the reduced junction resistance caused by the reduced band gap of silicon/germanium in the NMOS transistor (120, 220), an overall performance gain is accomplished, wherein, particularly in partially depleted SOI devices, the deleterious floating body effect is also reduced, due to the increased leakage currents generated by the silicon/germanium layer (117, 127, 217, 227) in the PMOS (110, 210) and NMOS transistor (120, 220).

公开(公告)号：WO2004032217A1

公开(公告)日：2004-04-15

申请号：PCT/US2003/029031

申请日：2003-09-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  KAMMLER, Thorsten ,  HORSTMANN, Manfred

IPC: H01L21/285

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/66507 ,  H01L29/6653

Abstract: The introduction of a barrier diffusion material, such as nitrogen, into a silicon-containing conductive region, for example the drain and source regions (204, 205) and the gate electrode (208) of a field effect transistor, allows the formation of nickel silicide (211, 212), which is substantially thermally stable up to temperatures of 500 °C. Thus, the device performance may significantly improve as the sheet resistance of nickel silicide is significantly less than that of nickel disilicide.

Abstract translation: 诸如氮的阻挡扩散材料引入含硅导电区域，例如场效应晶体管的漏极和源极区域（204,205）和栅电极（208），允许形成镍 硅化物（211,212），其在500℃的温度下基本上是热稳定的。 因此，随着硅化镍的薄层电阻显着小于二硅化镍的电阻，器件性能可能显着提高。

公开(公告)号：WO2008121326A2

公开(公告)日：2008-10-09

申请号：PCT/US2008/004065

申请日：2008-03-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  WEI, Andy ,  KAMMLER, Thorsten ,  BOSCHKE, Roman ,  SCOTT, Casey

Inventor： WEI, Andy ,  KAMMLER, Thorsten ,  BOSCHKE, Roman ,  SCOTT, Casey

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/84

CPC classification number: H01L29/6659 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

Abstract: By reconfiguring material (202, 302, 402) in a recess (210R, 310R, 410R) formed in drain and source regions (251, 351, 451) of SOI transistors (250, 350, 450), the depth of the recess (210R, 310R, 410R) may be increased down to the buried insulating layer (205, 305, 405) prior to forming respective metal suicide regions (254), thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element (250, 350, 450) is covered by a highly stressed dielectric material (203). The material redistribution may be accomplished on the basis of a high temperature hydrogen bake (211, 311) or an isotropic etch.

Abstract translation: 通过在SOI晶体管（250,350,450）的漏极和源极区域（251,351,451）中形成的凹槽（210R，310R，410R）中重新配置材料（202,302,402） ）之前，在形成相应的金属硅化物区域（254）之前，可以将凹陷（210R，310R，410R）的深度增加到埋置绝缘层（205,305,405），由此降低串联电阻并且增强应力传递 当相应的晶体管元件（250,350,450）被高应力介电材料（203）覆盖时。 材料再分布可以基于高温氢气烘烤（211,311）或各向同性蚀刻来完成。

公开(公告)号：WO2007130240A1

公开(公告)日：2007-11-15

申请号：PCT/US2007/007843

申请日：2007-03-29

Applicant: ADVANCED MICRO DEVICES , INC. ,  WEI, Andy ,  PEIDOUS, Igor ,  KAMMLER, Thorsten

Inventor： WEI, Andy ,  PEIDOUS, Igor ,  KAMMLER, Thorsten

IPC: H01L29/04 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/24 ,  H01L29/08

CPC classification number: H01L29/0847 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

Abstract: By appropriately orienting the channel length direction with respect to the crystallographic characteristics of a silicon layer (102), the stress-inducing effects of strained silicon/carbon material (109) may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel (103) may be oriented along the direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four.

Abstract translation: 通过相对于硅层（102）的晶体学特性适当地定向沟道长度方向，与常规技术相比，应变硅/碳材料（109）的应力诱导效应可以显着提高。 在一个说明性实施例中，通道（103）可以沿着<100>方向取向（100）表面取向，从而提供约四倍的电子迁移率增加。

公开(公告)号：WO2005022608A3

公开(公告)日：2005-03-10

申请号：PCT/US2004/028282

申请日：2004-08-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  PATTON, Jeffrey, P. ,  MAHANPOUR, Mehrdad ,  KAMMLER, Thorsten ,  BROWN, David, E. ,  BESSER, Paul, R. ,  CHAN, Simon, Siu-Sing ,  FRENKEL, Austin, C.

Inventor： PATTON, Jeffrey, P. ,  MAHANPOUR, Mehrdad ,  KAMMLER, Thorsten ,  BROWN, David, E. ,  BESSER, Paul, R. ,  CHAN, Simon, Siu-Sing ,  FRENKEL, Austin, C.

IPC: H01L21/336

Abstract: A method [900] of forming an integrated circuit [100] and a structure therefore is provided. A gate dielectric [104]is formed on a semiconductor substrate [102], and a gate [106] is formed over the gate dielectric [104]. Shallow source/drain junctions [304,306] are formed in the semiconductor substrate [102]. A sidewall spacer [402] is formed around the gate [106]. Deep source/drain junctions [504,506] are formed in the semiconductor substrate [102] using the sidewall spacer [402]. A siliciding spacer [610] is formed over the sidewall spacer [402] after forming the shallow and deep source/drain junctions [504,506]. A silicide [604] [606] is formed on the deep source/drain junctions [504,506] adjacent the siliciding spacer [610], and a dielectric layer [702] is deposited above the semiconductor substrate [102]. Contacts are then formed in the dielectric layer [702] to the silicide [604][606].

公开(公告)号：WO2005017992A1

公开(公告)日：2005-02-24

申请号：PCT/US2004/017705

申请日：2004-06-04

Applicant: ADVANCED MICRO DEVICES, INC. ,  WIECZOREK, Karsten ,  FEUDEL, Thomas ,  KAMMLER, Thorsten ,  BUCHHOLTZ, Wolfgang

Inventor： WIECZOREK, Karsten ,  FEUDEL, Thomas ,  KAMMLER, Thorsten ,  BUCHHOLTZ, Wolfgang

IPC: H01L21/336

CPC classification number: H01L29/66553 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/78618

Abstract: By forming an implantation mask (220) prior to the definition of the drain and the source areas (208), an effective decoupling of the gate dopant concentration from that of the drain and source concentrations is achieved. Moreover, after removal of the implantation mask (220), the lateral dimension of the gate electrode (205) may be defined by well-established sidewall spacer (207) techniques, thereby providing a scaling advantage with respect to conventional approaches based on photolithography and anisotropic etching.

Abstract translation: 通过在漏极和源极区域（208）的定义之前形成注入掩模（220），实现了栅极掺杂剂浓度与漏极和源极浓度的有效去耦。 此外，在移除注入掩模（220）之后，栅电极（205）的横向尺寸可以通过确定的侧壁间隔物（207）技术来限定，从而相对于基于光刻的常规方法提供缩放优点， 各向异性蚀刻。