公开(公告)号：WO2003083951A1

公开(公告)日：2003-10-09

申请号：PCT/US2002/041312

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  STEPHAN, Rolf

IPC: H01L29/36

CPC classification number: H01L21/823807 ,  H01L29/1033 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/6659

Abstract: An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.

Abstract translation: 在离子注入步骤之后在阱结构上提供外延生长的沟道层，并且进行热处理步骤以在阱结构中建立所需的掺杂剂分布。 根据需要，沟道层可以是未掺杂的或稍微掺杂的，使得与传统器件相比，沟道层中最终获得的掺杂剂浓度显着降低，从而在场效应晶体管的沟道区域中提供逆向掺杂物分布。 此外，可以在阱结构和沟道层之间提供阻挡扩散层，以在形成沟道层之后进行的任何热处理期间减小向上扩散。 可以通过沟道层的厚度，扩散阻挡层的厚度和组成以及在沟道层中引入掺杂剂原子的任何额外的注入步骤来调整沟道区中的最终掺杂物分布。

公开(公告)号：WO2009108370A1

公开(公告)日：2009-09-03

申请号：PCT/US2009/001287

申请日：2009-02-27

Applicant: ADVANCED MICRO DEVICES, INC. ,  WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  HUEBLER, Peter ,  RUTTLOFF, Kerstin

Inventor： WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  HUEBLER, Peter ,  RUTTLOFF, Kerstin

IPC: H01L21/768 ,  H01L21/8238

CPC classification number: H01L21/76826 ,  H01L21/76832 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L29/7843 ,  Y02P80/30

Abstract: In a dual stress liner approach, an intermediate etch stop material (234) may be provided on the basis of a plasma-assisted oxidation process (250) rather than by deposition so the corresponding thickness (234T) of the etch stop material (234) may be reduced. Consequently, the resulting aspect ratio may be less pronounced compared to conventional strategies, thereby reducing deposition-related irregularities which may translate into a significant reduction of yield loss, in particular for highly scaled semiconductor devices (200).

Abstract translation: 在双重应力衬里方法中，可以基于等离子体辅助氧化工艺（250）而不是通过沉积来提供中间蚀刻停止材料（234），使得蚀刻停止材料（234）的对应厚度（234T） 可能会减少。 因此，与常规策略相比，所产生的纵横比可能不那么明显，从而减少沉积相关的不规则性，这可能转化为产量损失的显着降低，特别是对于高度缩放的半导体器件（200）。

公开(公告)号：WO2007100589A1

公开(公告)日：2007-09-07

申请号：PCT/US2007/004544

申请日：2007-02-20

Applicant: ADVANCED MICRO DEVICES, INC. ,  WEI, Andy ,  KAMMLER, Thorsten ,  HOENTSCHEL, Jan ,  HORSTMANN, Manfred

Inventor： WEI, Andy ,  KAMMLER, Thorsten ,  HOENTSCHEL, Jan ,  HORSTMANN, Manfred

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: By removing a portion of a halo region (206, 306) or by avoiding the formation of the halo region (206, 306) within the extension region (209A), which may be subsequently formed on the basis of a re-grown semiconductor material (218, 318), the threshold roll off behavior may be significantly improved, wherein an enhanced current drive capability may simultaneously be achieved.

Abstract translation: 通过去除一部分卤素区域（206,306）或通过避免在扩展区域（209A）内形成卤区域（206,306），其可以随后基于重新生长的半导体材料形成 （218,318），可以显着改善阈值滚降行为，其中可以同时实现增强的电流驱动能力。

公开(公告)号：WO2006049834A1

公开(公告)日：2006-05-11

申请号：PCT/US2005/036779

申请日：2005-10-12

Applicant: ADVANCED MICRO DEVICES, INC. ,  HORSTMANN, Manfred ,  PRUEFER, Ekkehard ,  BUCHHOLTZ, Wolfgang

Inventor： HORSTMANN, Manfred ,  PRUEFER, Ekkehard ,  BUCHHOLTZ, Wolfgang

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/265

CPC classification number: H01L29/6659 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

Abstract: By locally modifying the intrinsic stress of a dielectric layer laterally enclosing gate electrode structures of a transistor configuration formed in accordance with in-laid gate techniques, the charge carrier mobility of different transistor elements may individually be adjusted. In particular, in in-laid gate structure transistor architecture, NMOS transistors and PMOS transistors may receive a tensile and a compressive stress, respectively.

Abstract translation: 通过局部改变根据叠层栅极技术形成的晶体管配置的横向包围栅电极结构的电介质层的固有应力，可以单独地调节不同晶体管元件的电荷载流子迁移率。 特别地，在嵌入式栅结构晶体管架构中，NMOS晶体管和PMOS晶体管可以分别接收拉伸和压缩应力。

公开(公告)号：WO2003083936A1

公开(公告)日：2003-10-09

申请号：PCT/US2002/040806

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  KAHLERT, Volker ,  HORSTMANN, Manfred

IPC: H01L21/768

CPC classification number: H01L21/28518 ,  H01L21/28052 ,  H01L21/76841 ,  H01L29/4933 ,  H01L29/665

Abstract: A layer stack (220) comprising at least three material layers (221, 222, and 223) is provided on a silicon-containing conductive region to form a silicide portion (208) on and in the silicon-containing conductive region, wherein the layer (221) next to the silicon provides the metal atoms for the silicide reaction, the intermediate layer (222) is a metal-nitrogen-compound formed by supplying a nitrogen containing as during deposition, and for formation of the top layer (223), supply for said gas is discontinued. The method may be carried out as an in situ method, thereby significantly improving throughput and deposition tool performance compared to typical prior art processes, in which at least two deposition chambers have to be used

Abstract translation: 包含至少三个材料层（221,222和223）的层叠体（220）设置在含硅导电区域上以在含硅导电区域上和之中形成硅化物部分（208），其中层 （221）提供了用于硅化物反应的金属原子，中间层（222）是通过在沉积期间提供含氮并形成顶层（223）而形成的金属氮化合物， 所述气体的供给被停止。 该方法可以作为原位方法进行，从而与典型的现有技术方法相比显着提高生产量和沉积工具性能，其中必须使用至少两个沉积室

公开(公告)号：WO2006022946A1

公开(公告)日：2006-03-02

申请号：PCT/US2005/018357

申请日：2005-05-25

Applicant: ADVANCED MICRO DEVICES, INC. ,  WIRBELEIT, Frank ,  BURBACH, Gert ,  WIECZOREK, Karsten ,  HORSTMANN, Manfred

Inventor： WIRBELEIT, Frank ,  BURBACH, Gert ,  WIECZOREK, Karsten ,  HORSTMANN, Manfred

IPC: H01L23/544

CPC classification number: H01L22/34

Abstract: By providing a test structure (100) including a plurality of test pads (104), the anisotropic behavior of stress and strain influenced electrical characteristics, such as the electron mobility, may be determined in a highly efficient manner. Moreover, the test pads (104) may enable the detection of stress and strain induced modifications with a spatial resolution in the order of magnitude of individual circuit elements.

Abstract translation: 通过提供包括多个测试焊盘（104）的测试结构（100），可以以高效的方式确定应力和应变影响的电特性（例如电子迁移率）的各向异性行为。 此外，测试焊盘（104）可以以单个电路元件的数量级的空间分辨率来检测应力和应变诱发的修改。

公开(公告)号：WO2006022915A1

公开(公告)日：2006-03-02

申请号：PCT/US2005/015294

申请日：2005-04-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  WIRBELEIT, Frank ,  HORSTMANN, Manfred ,  HOBERT, Christian

Inventor： WIRBELEIT, Frank ,  HORSTMANN, Manfred ,  HOBERT, Christian

IPC: H01L29/78

CPC classification number: G11C11/412 ,  H01L27/11

Abstract: By providing a self-biasing semiconductor switch, an SRAM cell (450) having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor (400) that allows the formation of an SRAM cell (450) with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.

Abstract translation: 通过提供自偏压半导体开关，可以实现具有减少数量的各个有源元件的SRAM单元（450）。 在特定实施例中，自偏置半导体器件可以以双通道场效应晶体管（400）的形式提供，其允许形成具有小于六个晶体管元件的SRAM单元（450），并且在优选实施例中， 只有两个单独的晶体管元件。

公开(公告)号：WO2003079424A1

公开(公告)日：2003-09-25

申请号：PCT/US2002/041089

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  STEPHAN, Rolf

IPC: H01L21/28

CPC classification number: H01L21/823443 ,  H01L21/823418 ,  H01L29/665

Abstract: A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may be significantly improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.

Abstract translation: 公开了一种方法，其中不同的金属层依次沉积在含硅区域上，使得金属层的类型和厚度可以适应于下面的含硅区域的特定特性。 随后，进行热处理以将金属转化为金属硅化物，从而提高含硅区域的导电性。 以这种方式，可以形成独立地适应特定的含硅区域的硅化物部分，从而可以显着改善各个半导体元件的器件性能或多个半导体元件的整体性能。 此外，公开了一种半导体器件，其包括至少两个其中形成有不同硅化物部分的含硅区域，其中至少一个硅化物部分包括贵金属。

公开(公告)号：WO2003075326A2

公开(公告)日：2003-09-12

申请号：PCT/US2002/041142

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： STEPHAN, Rolf ,  HORSTMANN, Manfred ,  WIECZOREK, Karsten

IPC: H01L21/00

CPC classification number: H01L21/324 ,  H01L21/28052 ,  H01L21/823835 ,  H01L21/823842

Abstract: In a method for fabricating a semiconductor device different types of a metal-semiconductor compound (241, 261) are formed on or in at least two different conductive semiconductor regions so that for each semiconductor region the metal-semiconductor compound region may be formed to obtain an optimum overall performance of the semiconductor device. On one of the two semiconductor regions, the metal-semiconductor compound is formed of at least two different metal layers (240, 260), whereas the metal-semiconductor compound in or on the other semiconductor region is formed from a single metal layer (240).

Abstract translation: 在制造半导体器件的方法中，在至少两个不同的导电半导体区域上形成不同类型的金属 - 半导体化合物（241,261），使得对于每个半导体区域，可以形成金属 - 半导体化合物区域以获得 半导体器件的最佳整体性能。 在两个半导体区域中的一个上，金属 - 半导体化合物由至少两个不同的金属层（240,260）形成，而另一个半导体区域中或另一个半导体区域中的金属 - 半导体化合物由单个金属层（240 ）。

公开(公告)号：WO2009134412A1

公开(公告)日：2009-11-05

申请号：PCT/US2009/002669

申请日：2009-04-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  HORSTMANN, Manfred ,  JAVORKA, Peter ,  WIECZOREK, Karsten ,  RUTTLOFF, Kerstin

Inventor： HORSTMANN, Manfred ,  JAVORKA, Peter ,  WIECZOREK, Karsten ,  RUTTLOFF, Kerstin

IPC: H01L21/8238 ,  H01L21/02

CPC classification number: H01L21/823828 ,  H01L21/02068 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823835 ,  H01L21/823871

Abstract: A method is disclosed which includes implanting an inert species in a layer of a gate electrode material (205A), the gate electrode material being formed above a substrate (201) and having a P-doped layer portion and an N-doped layer portion, forming a first gate electrode (205P) from the P-doped layer portion and a second gate electrode (205N) from the N-doped layer portion, performing a wet chemical cleaning process, and forming a first transistor (200B) on the basis of the first gate electrode (205P) and a second transistor (200A) on the basis of the second gate electrode (205N).

Abstract translation: 公开了一种方法，其包括在栅电极材料（205A）的层中注入惰性物质，栅电极材料形成在衬底（201）上方并具有P掺杂层部分和N掺杂层部分， 从所述P掺杂层部分形成第一栅电极（205P），从所述N掺杂层部分形成第二栅电极（205N），进行湿化学清洗处理，以及基于 基于第二栅电极（205N）的第一栅电极（205P）和第二晶体管（200A）。