公开(公告)号：WO2008016512A1

公开(公告)日：2008-02-07

申请号：PCT/US2007/016612

申请日：2007-07-24

Applicant: ADVANCED MICRO DEVICES, INC. ,  WIRBELEIT, Frank ,  WEI, Andy ,  BOSCHKE, Roman

Inventor： WIRBELEIT, Frank ,  WEI, Andy ,  BOSCHKE, Roman

IPC: H01L29/10

CPC classification number: H01L29/66636 ,  H01L21/02238 ,  H01L21/26506 ,  H01L21/28185 ,  H01L21/2822 ,  H01L21/31662 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/105 ,  H01L29/665 ,  H01L29/66651 ,  H01L29/7848

Abstract: By forming a semiconductor alloy (107, 107A, 107B, 207A, 207B, 307) in a silicon-based active semiconductor region prior to the gate patterning, material characteristics of the semiconductor alloy itself may also be exploited in addition to the strain-inducing effect thereof. Consequently, device performance of advanced field effect transistors may be even further enhanced compared to conventional approaches using a strained semiconductor alloy in the drain and source regions.

Abstract translation: 通过在栅极图案化之前在硅基有源半导体区域中形成半导体合金（107,107A，107B，207A，207B，307），除了应变诱导之外，还可以利用半导体合金本身的材料特性 效果。 因此，与在漏极和源极区域中使用应变半导体合金的常规方法相比，先进的场效应晶体管的器件性能可以进一步提高。

公开(公告)号：WO2007053382A1

公开(公告)日：2007-05-10

申请号：PCT/US2006/041560

申请日：2006-10-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  HOENTSCHEL, Jan ,  WEI, Andy ,  HORSTMANN, Manfred ,  KAMMLER, Thorsten

Inventor： HOENTSCHEL, Jan ,  WEI, Andy ,  HORSTMANN, Manfred ,  KAMMLER, Thorsten

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/04 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/78618 ,  H01L29/78639 ,  H01L29/78654

Abstract: By forming a deep recess (111, 211) through the buried insulating layer (103, 203) and re-growing a strained semiconductor material (112, 212), an enhanced strain generation mechanism may be provided in SOI- like transistors (100, 200). Consequently, the strain may also be efficiently created by the embedded strained semiconductor material across the entire active layer, thereby significantly enhancing the performance of transistor devices, in which two channel regions may be defined.

Abstract translation: 通过形成通过掩埋绝缘层（103,203）的深凹槽（111,211）并重新生长应变半导体材料（112,212），增强的应变产生机构可以设置在类SOI晶体管（100， 200）。 因此，也可以通过整个有源层上的嵌入的应变半导体材料有效地产生应变，从而显着提高可以限定两个沟道区的晶体管器件的性能。

公开(公告)号：WO2006083546A2

公开(公告)日：2006-08-10

申请号：PCT/US2006/001596

申请日：2006-01-17

Applicant: ADVANCED MICRO DEVICES, INC. ,  KAMMLER, Thorsten ,  WEI, Andy ,  BIERSTEDT, Helmut

Inventor： KAMMLER, Thorsten ,  WEI, Andy ,  BIERSTEDT, Helmut

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L21/26586 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: By performing a sequence of selective epitaxial growth processes with at least two different species, or by introducing a first dopant species prior to the epitaxial growth of a drain and source region, a halo region may be formed in a highly efficient manner, while at the same time the degree of lattice damage in the epitaxially grown semiconductor region is maintained at a low level. The method ??? forming a first semiconductor region 211 by a first epitaxial growth process, forming a second semiconductor region 210 by performing a second epitaxial growth process, whereas the first and second semiconductor regions compose different dopant species.

Abstract translation: 通过用至少两种不同的物质执行一系列选择性外延生长过程，或者通过在漏极和源极区的外延生长之前引入第一掺杂物种，可以以高效的方式形成晕圈，而在 同时，外延生长的半导体区域中的晶格损伤程度保持在低水平。 方法 ？？？ 通过第一外延生长工艺形成第一半导体区域211，通过执行第二外延生长工艺形成第二半导体区域210，而第一和第二半导体区域构成不同的掺杂物质。

公开(公告)号：WO2003075357A1

公开(公告)日：2003-09-12

申请号：PCT/US2002/040745

申请日：2002-12-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WEI, Andy ,  SULTAN, Akif ,  WU, David

IPC: H01L29/786

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/26593 ,  H01L21/3221 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78621

Abstract: Various circuit devices (14, 16 and 18) incorporating junction-traversing dislocation regions (60, 64 or 66) and methods of making the same are provided. In one aspect, a method of processing is provided that includes forming an impurity region (42) in a device region (20) of a semiconductor-on-insulator substrate (12). The impurity region (42) defines a junction (56). A dislocation region (64) is formed in the device region (20) that traverses the junction, (56). The dislocation region (64) provides a pathway to neutralize charge lingering in a floating body of a device.

Abstract translation: 提供了结合穿越位错区域60,64或66的各种电路装置14,16和18及其制造方法。 在一个方面，提供了一种处理方法，其包括在绝缘体上半导体衬底12的器件区域20中形成杂质区域42.杂质区域42限定结56.位错区域64形成在器件 区域20穿过接头56.位错区域64提供中和在设备的浮体中滞留的电荷的路径。

公开(公告)号：WO2010049086A3

公开(公告)日：2010-05-06

申请号：PCT/EP2009/007548

申请日：2009-10-21

Applicant: ADVANCED MICRO DEVICES, INC. ,  GRIEBENOW, Uwe ,  WEI, Andy ,  HOENTSCHEL, Jan ,  SCHEIPER,Thilo

Inventor： GRIEBENOW, Uwe ,  WEI, Andy ,  HOENTSCHEL, Jan ,  SCHEIPER,Thilo

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/165 ,  H01L29/417 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8238

Abstract: During the manufacturing process for forming sophisticated transistor elements, the gate height may be reduced and also a recessed drain and source configuration may be obtained in a common etch sequence prior to forming respective metal suicide regions. Since the corresponding sidewall spacer structure may be maintained during the etch sequence, controllability and uniformity of the silicidation process in the gate electrode may be enhanced, thereby obtaining a reduced degree of threshold variability. Furthermore, the recessed drain and source configuration may provide for reduced overall series resistance and enhanced stress transfer efficiency.

公开(公告)号：WO2010037522A1

公开(公告)日：2010-04-08

申请号：PCT/EP2009/007001

申请日：2009-09-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  MULFINGER, Robert ,  WEI, Andy ,  HOENTSCHEL, Jan ,  SCOTT, Casey

Inventor： MULFINGER, Robert ,  WEI, Andy ,  HOENTSCHEL, Jan ,  SCOTT, Casey

IPC: H01L21/336 ,  H01L29/04 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/78

Abstract: In sophisticated semiconductor devices a strain inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behaviour with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behaviour, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide for the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability.

Abstract translation: 在复杂的半导体器件中，应变诱导半导体合金可以通过基于湿化学蚀刻工艺形成空腔来定位，靠近沟道区域，其可以具有相对于不同晶体取向的各向异性蚀刻行为。 在一个实施方案中，可以使用TMAH，除了各向异性蚀刻行为之外，还显示出相对于二氧化硅的高蚀刻选择性，从而实现极薄的蚀刻停止层，其另外提供进一步减少来自通道的偏移的可能性 区域，而不会不利地导致整体过程变化。

公开(公告)号：WO2010022972A1

公开(公告)日：2010-03-04

申请号：PCT/EP2009/006261

申请日：2009-08-28

Applicant: ADVANCED MICRO DEVICES INC. ,  HOENTSCHEL, Jan ,  WEI, Andy ,  BEYER, Sven

Inventor： HOENTSCHEL, Jan ,  WEI, Andy ,  BEYER, Sven

IPC: H01L21/336 ,  H01L21/84 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/7846 ,  H01L21/7624 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849

Abstract: In a strained SOI semiconductor layer the stress relaxation which may typically occur during the patterning of trench isolation structures may be reduced by selecting an appropriate reduced target height of the active regions, thereby enabling the formation of transistor elements on the active region of reduced height, which may still include a significant amount of the initial strained component. The active regions of reduced height may advantageously be used for forming fully depleted field effect transistors.

Abstract translation: 在应变SOI半导体层中，可以通过选择适当的有源区的目标高度来减小在沟槽隔离结构的图形化期间通常发生的应力松弛，由此能够在减小的高度的有源区上形成晶体管元件， 这仍然可能包括大量的初始应变成分。 降低高度的有源区可以有利地用于形成完全耗尽的场效应晶体管。

公开(公告)号：WO2008121326A2

公开(公告)日：2008-10-09

申请号：PCT/US2008/004065

申请日：2008-03-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  WEI, Andy ,  KAMMLER, Thorsten ,  BOSCHKE, Roman ,  SCOTT, Casey

Inventor： WEI, Andy ,  KAMMLER, Thorsten ,  BOSCHKE, Roman ,  SCOTT, Casey

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/84

CPC classification number: H01L29/6659 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

Abstract: By reconfiguring material (202, 302, 402) in a recess (210R, 310R, 410R) formed in drain and source regions (251, 351, 451) of SOI transistors (250, 350, 450), the depth of the recess (210R, 310R, 410R) may be increased down to the buried insulating layer (205, 305, 405) prior to forming respective metal suicide regions (254), thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element (250, 350, 450) is covered by a highly stressed dielectric material (203). The material redistribution may be accomplished on the basis of a high temperature hydrogen bake (211, 311) or an isotropic etch.

Abstract translation: 通过在SOI晶体管（250,350,450）的漏极和源极区域（251,351,451）中形成的凹槽（210R，310R，410R）中重新配置材料（202,302,402） ）之前，在形成相应的金属硅化物区域（254）之前，可以将凹陷（210R，310R，410R）的深度增加到埋置绝缘层（205,305,405），由此降低串联电阻并且增强应力传递 当相应的晶体管元件（250,350,450）被高应力介电材料（203）覆盖时。 材料再分布可以基于高温氢气烘烤（211,311）或各向同性蚀刻来完成。

公开(公告)号：WO2007130240A1

公开(公告)日：2007-11-15

申请号：PCT/US2007/007843

申请日：2007-03-29

Applicant: ADVANCED MICRO DEVICES , INC. ,  WEI, Andy ,  PEIDOUS, Igor ,  KAMMLER, Thorsten

Inventor： WEI, Andy ,  PEIDOUS, Igor ,  KAMMLER, Thorsten

IPC: H01L29/04 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/24 ,  H01L29/08

CPC classification number: H01L29/0847 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

Abstract: By appropriately orienting the channel length direction with respect to the crystallographic characteristics of a silicon layer (102), the stress-inducing effects of strained silicon/carbon material (109) may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel (103) may be oriented along the direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four.

Abstract translation: 通过相对于硅层（102）的晶体学特性适当地定向沟道长度方向，与常规技术相比，应变硅/碳材料（109）的应力诱导效应可以显着提高。 在一个说明性实施例中，通道（103）可以沿着<100>方向取向（100）表面取向，从而提供约四倍的电子迁移率增加。

公开(公告)号：WO2007064472A1

公开(公告)日：2007-06-07

申请号：PCT/US2006/044292

申请日：2006-11-15

Applicant: ADVANCED MICRO DEVICES, INC. ,  HOENTSCHEL, Jan ,  WEI, Andy ,  HEINZE, Mario ,  JAVORKA, Peter

Inventor： HOENTSCHEL, Jan ,  WEI, Andy ,  HEINZE, Mario ,  JAVORKA, Peter

IPC: H01L21/336 ,  H01L21/265

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848

Abstract: By performing a tilted amorphization implantation (208, 308P, 308N) and a subsequent re-crystallization on the basis of a stressed overlying material (209, 211, 309, 311, 319S), a highly efficient strain-inducing mechanism is provided. The tilted amorphization implantation (208, 308P, 308N) may result in a significantly reduced defect rate during the re-crystallization process, thereby substantially reducing leakage currents in sophisticated transistor elements (200, 300N, 300P).

Abstract translation: 通过基于应力覆盖材料（209,211,309,311,319S）进行倾斜非晶化注入（208,308P，308N）和随后的重结晶，提供了一种高效应变诱发机制。 倾斜的非晶化注入（208,308P，308N）可能导致在再结晶过程期间显着降低的缺陷率，从而大大降低复杂晶体管元件（200,300N，300P）中的漏电流。