公开(公告)号：WO2003075357A1

公开(公告)日：2003-09-12

申请号：PCT/US2002/040745

申请日：2002-12-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WEI, Andy ,  SULTAN, Akif ,  WU, David

IPC: H01L29/786

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/26593 ,  H01L21/3221 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78621

Abstract: Various circuit devices (14, 16 and 18) incorporating junction-traversing dislocation regions (60, 64 or 66) and methods of making the same are provided. In one aspect, a method of processing is provided that includes forming an impurity region (42) in a device region (20) of a semiconductor-on-insulator substrate (12). The impurity region (42) defines a junction (56). A dislocation region (64) is formed in the device region (20) that traverses the junction, (56). The dislocation region (64) provides a pathway to neutralize charge lingering in a floating body of a device.

Abstract translation: 提供了结合穿越位错区域60,64或66的各种电路装置14,16和18及其制造方法。 在一个方面，提供了一种处理方法，其包括在绝缘体上半导体衬底12的器件区域20中形成杂质区域42.杂质区域42限定结56.位错区域64形成在器件 区域20穿过接头56.位错区域64提供中和在设备的浮体中滞留的电荷的路径。

公开(公告)号：WO2003054952A1

公开(公告)日：2003-07-03

申请号：PCT/US2002/041331

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BULLER, James, F. ,  WU, David ,  LUNING, Scott ,  WRISTERS, Derick, J. ,  KADOSH, Daniel

IPC: H01L21/336

CPC classification number: H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

Abstract: Semiconductor devices with improved transistor performance are fabricated by forming a composite oxide/nitride liner (24,25) under a gate electrode sidewall spacer (40). Embodiements include depositing a conformal oxide layer (24) by decoupled plasma deposition, depositing a conformal nitride layer (25) by decoupled plasma deposition, depositing a spacer layer (30) and then etching.

Abstract translation: 具有改善的晶体管性能的半导体器件通过在栅电极侧壁间隔物（40）下形成复合氧化物/氮化物衬垫（24,25）来制造。 实例包括通过解耦等离子体沉积沉积保形氧化物层（24），通过解耦等离子体沉积沉积共形氮化物层（25），沉积间隔层（30）然后蚀刻。

公开(公告)号：EP1456877B1

公开(公告)日：2010-07-21

申请号：EP02796042.6

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BULLER, James, F. ,  WU, David ,  LUNING, Scott ,  WRISTERS, Derick, J. ,  KADOSH, Daniel

IPC: H01L21/336 ,  H01L29/49

CPC classification number: H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

公开(公告)号：EP1456877A1

公开(公告)日：2004-09-15

申请号：EP02796042.6

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： BULLER, James, F. ,  WU, David ,  LUNING, Scott ,  WRISTERS, Derick, J. ,  KADOSH, Daniel

IPC: H01L21/336

CPC classification number: H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

Abstract: Semiconductor devices with improved transistor performance are fabricated by forming a composite oxide/nitride liner (24,25) under a gate electrode sidewall spacer (40). Embodiements include depositing a conformal oxide layer (24) by decoupled plasma deposition, depositing a conformal nitride layer (25) by decoupled plasma deposition, depositing a spacer layer (30) and then etching.

公开(公告)号：EP1330838A1

公开(公告)日：2003-07-30

申请号：EP01957270.0

申请日：2001-07-26

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： AMINPUR, Massud ,  WU, David ,  LUNING, Scott

IPC: H01L21/28

CPC classification number: H01L21/28123 ,  H01L29/6659

Abstract: A method is provided, the method including forming a gate dielectric layer (510) above a substrate layer ((505), forming a gate conductor layer (515) above the gate dielectric layer (510), forming a first hard mask layer (540). The method also includes forming a trimmed photoresist mark (570) above the second hard mask layer (550), and forming a patterned hard mask (650) in the second hard mask layer (550) using the trimmed photoresist mask (570) to remove portions (655) of the second hard mask layer (550), the patterned hard mask (650) having a first dimension (δtrim). The method further includes forming a selectively etched hard mask (740) in the first hard mask layer (540) by removing portions (745) of the first hard mask layer (540) adjacent the patterned hard mask (650), the selectively etched hard mask (740) having a second dimension (Δ) less than the first dimension (δtrim), and forming a structure (800) using the selectively etched hard mask (740) to remove portions of the gate conductor layer (515) above the gate dielectric layer (510).

公开(公告)号：EP1330838B1

公开(公告)日：2010-12-01

申请号：EP01957270.0

申请日：2001-07-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： AMINPUR, Massud ,  WU, David ,  LUNING, Scott

IPC: H01L21/28

CPC classification number: H01L21/28123 ,  H01L29/6659

Abstract: A method is provided, the method including forming a gate dielectric layer (510) above a substrate layer ((505), forming a gate conductor layer (515) above the gate dielectric layer (510), forming a first hard mask layer (540). The method also includes forming a trimmed photoresist mark (570) above the second hard mask layer (550), and forming a patterned hard mask (650) in the second hard mask layer (550) using the trimmed photoresist mask (570) to remove portions (655) of the second hard mask layer (550), the patterned hard mask (650) having a first dimension (δtrim). The method further includes forming a selectively etched hard mask (740) in the first hard mask layer (540) by removing portions (745) of the first hard mask layer (540) adjacent the patterned hard mask (650), the selectively etched hard mask (740) having a second dimension (Δ) less than the first dimension (δtrim), and forming a structure (800) using the selectively etched hard mask (740) to remove portions of the gate conductor layer (515) above the gate dielectric layer (510).