公开(公告)号：WO2003075357A1

公开(公告)日：2003-09-12

申请号：PCT/US2002/040745

申请日：2002-12-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WEI, Andy ,  SULTAN, Akif ,  WU, David

IPC: H01L29/786

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/26593 ,  H01L21/3221 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78621

Abstract: Various circuit devices (14, 16 and 18) incorporating junction-traversing dislocation regions (60, 64 or 66) and methods of making the same are provided. In one aspect, a method of processing is provided that includes forming an impurity region (42) in a device region (20) of a semiconductor-on-insulator substrate (12). The impurity region (42) defines a junction (56). A dislocation region (64) is formed in the device region (20) that traverses the junction, (56). The dislocation region (64) provides a pathway to neutralize charge lingering in a floating body of a device.

Abstract translation: 提供了结合穿越位错区域60,64或66的各种电路装置14,16和18及其制造方法。 在一个方面，提供了一种处理方法，其包括在绝缘体上半导体衬底12的器件区域20中形成杂质区域42.杂质区域42限定结56.位错区域64形成在器件 区域20穿过接头56.位错区域64提供中和在设备的浮体中滞留的电荷的路径。

公开(公告)号：WO2007015930A1

公开(公告)日：2007-02-08

申请号：PCT/US2006/028171

申请日：2006-07-20

Applicant: ADVANCED MICRO DEVICES, INC. ,  PEIDOUS, Igor ,  SULTAN, Akif ,  PELELLA, Mario, M.

Inventor： PEIDOUS, Igor ,  SULTAN, Akif ,  PELELLA, Mario, M.

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

Abstract: Methods are provided for fabricating a stressed MOS device [30]. The method comprises the steps of forming a plurality of parallel MOS transistors in and on a semiconductor substrate [36]. The parallel MOS transistors having a common source [92] region, a common drain [94] region, and a common gate electrode [66]. A first trench [82] is etched into the substrate in the common source [92] region and a second trench [84] is etched into the substrate in the common drain [94] region. A stress inducing semiconductor material [90] that has a crystal lattice mismatched with the semiconductor substrate is selectively grown in the first [82] and second [84] trenches. The growth of the stress inducing material [90] creates both compressive longitudinal and tensile transverse stresses in the MOS device channel [50] that enhance the drive current of P-channel MOS transistors. The decrease in drive current of N-channel MOS transistors caused by the compressive stress component is offset by the tensile stress component.

Abstract translation: 提供了制造应力MOS器件的方法[30]。 该方法包括以下步骤：在半导体衬底上形成多个并联MOS晶体管[36]。 并联MOS晶体管具有公共源极区域，公共漏极区域和公共栅极电极[66]。 第一沟槽[82]被蚀刻到公共源极区域中的衬底中，并且第二沟槽[84]被蚀刻到公共漏极[94]区域中的衬底中。 在第一[82]和第二[84]沟槽中选择性地生长具有与半导体衬底失配的晶格的应力诱导半导体材料[90]。 应力诱导材料的生长[90]在MOS器件通道[50]中产生压缩纵向和拉伸横向应力，从而增强P沟道MOS晶体管的驱动电流。 由压缩应力分量引起的N沟道MOS晶体管的驱动电流的减小由拉应力分量抵消。

公开(公告)号：EP1068637A1

公开(公告)日：2001-01-17

申请号：EP98960360.0

申请日：1998-11-24

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SULTAN, Akif

IPC: H01L21/336 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/6656 ,  H01L29/7836

Abstract: A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (56) with a sub-amorphous large tilt angle implant to thereby supply interstitials (62) at a location under the gate oxide (54). The method also includes forming a lightly doped drain extension region (66) in the drain region (58) of the substrate (56) and forming a drain (70) in the drain region (58) and forming a source extension region (67) and a source (72) in a source region (60) of the substrate (56). Lastly, the method includes thermally treating the substrate (56), wherein the interstitials (62) enhance a lateral diffusion (84) under the gate oxide (54) without substantially impacting a vertical diffusion (86) of the extension regions (66, 67), thereby reducing the effective channel length without an increase in a junction depth of the drain (70) and the drain extension region (66) or the source (72) and the source extension region (67).