公开(公告)号：EP1573746A1

公开(公告)日：2005-09-14

申请号：EP03812759.3

申请日：2003-07-24

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： LE, Binh, Q. ,  ACHTER, Michael ,  CLEVELAND, Lee

IPC: G11C16/26 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0491

Abstract: A memory circuit arrangement for sensing current in a target cell (305) during a read operation is disclosed. According to one exemplary embodiment, the memory circuit arrangement comprises the target cell (305) and a first neighboring cell (355) adjacent to the target cell (305). The first target cell (305) has a first bit line (316) connected to ground (365); the target cell (305) also has a second bit line (321) connected to a sensing circuit (360). The first neighboring cell (355) shares the second bit line (321) with the target cell (305); the first neighboring cell (355) also has a third bit line (341) connected to the sensing circuit (360) during the read operation. The memory circuit arrangement results in increased error margins in a fast and accurate manner during the read operation of the target cell (305).

公开(公告)号：EP1307965A1

公开(公告)日：2003-05-07

申请号：EP01950703.7

申请日：2001-06-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CLEVELAND, Lee ,  NGUYEN, Kendra

IPC: H03K19/017

CPC classification number: H03K19/01707

Abstract: An input buffer circuit (300) for a semiconductor device that includes a PMOS transistor (306), an NMOS transistor (308), and a pull-up circuit (314). The pull-up circuit (314) applies a voltage to the bulk region of the PMOS transistor (306) causing a positive body effect which causes the absolute value of the voltage threshold of the PMOS transistor (306) to temporally lower when the input buffer (300) switches. This causes the input buffer (300) to switch faster than conventional input buffers. The input buffer (300) is an inverter, NOR, NAND, or other input buffer.

公开(公告)号：EP1290559A2

公开(公告)日：2003-03-12

申请号：EP01939217.4

申请日：2001-05-21

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： AL-SHAMMA, Ali ,  CLEVELAND, Lee

IPC: G06F11/20

CPC classification number: G11C29/789 ,  G11C8/16 ,  G11C15/046

Abstract: A flash memory having redundancy content addressable memory (CAM) circuitry (106) is described. The flash memory is capable of substituting a second memory cell for an inoperative memory cell. The flash memory includes a primary array (118, 120, 122, 124, 134, 136, 138, 140) of memory cells, a redundant array (126, 128, 130, 132, 142, 144, 146, 148) of memory cells, and the redundancy CAM circuitry (106). The redundancy CAM circuitry (106) includes a plurality of dual-ported CAM stages (200). Each CAM stage (200) includes a CAM cell (202), a write data bus (204) coupled to the CAM cell (202), and a read data bus (206) coupled to the CAM cell (202). The CAM cell (202) stores information regarding a location of an inoperative memory cell in the primary array (118, 120, 122, 124, 134, 138, 140). The inoperative memory cell requires a substitution with a second memory cell in the redundant array (126, 128, 130, 132, 142, 144, 146, 148). The write data bus (204) produces the information from the CAM cell (202) responsively to a write select signal (WSELm). The write select signal (WSELm) is indicative of a write operation to be performed at memory cell locations in the primary array (18, 120, 122, 124, 134, 136, 138, 140). The read data bus (206) produces the information from the CAM cell (202) responsively to a read select signal (RSELm). The read select signal (RSELm) is indicative of a read operation to be performed at memory cell locations in the primary array (118, 120, 122, 124, 134, 136, 138, 140).

公开(公告)号：EP1256117A1

公开(公告)日：2002-11-13

申请号：EP00983940.8

申请日：2000-12-05

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CLEVELAND, Lee

IPC: G11C16/14

CPC classification number: G11C16/14

Abstract: A method to reduce the peak electric field during erase of a memory device composed of multiple memory cells. The electric field Efield of the memory cell during erase is determined by the equation Efield SIMILAR a g(Vgate - Vth) + Vtuv + ( a s -1)Vsource and varying gate voltages Vgate are applied to the gate of the cell being erased so that the Vgate - Vth is constant during the erase procedure.

公开(公告)号：EP0857346A1

公开(公告)日：1998-08-12

申请号：EP96921742.0

申请日：1996-06-21

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CLEVELAND, Lee ,  CHANG, Chung, K. ,  TANG, Yuan ,  LEONG, Nancy ,  FLIESLER, Michael ,  KUO, Tiao-Hua

IPC: G11C16

CPC classification number: G11C16/3409 ,  G11C16/3404 ,  G11C16/3445

Abstract: An integrated circuit including an array of flash EEPROM memory cells wherein overerase correction is provided after application of each erase pulse.

公开(公告)号：EP1563507A1

公开(公告)日：2005-08-17

申请号：EP03811992.1

申请日：2003-07-10

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： LE, Binh, Quang ,  CLEVELAND, Lee ,  CHEN, Pau-Ling

IPC: G11C7/12 ,  G11C16/24

CPC classification number: G11C16/24 ,  G11C7/067

Abstract: A cascode amplifier circuit (205), which generates a fast, stable and accurate bit line voltage (230), is disclosed. According to one exemplary embodiment, the cascode amplifier circuit (205) comprises a transistor (210) having a source connected to a bit line voltage (230) and a drain connected to an output voltage (225). The cascode amplifier circuit (205) also comprises a differential circuit (212) having an inverting input (215) connected to the bit line voltage (230), a non-inverting input connected to a reference voltage (202), and an output (280) connected to a gate of the first transistor (210). The operation of the transistor (210) and the differential circuit (212) generate a fast, stable the accurate bit line voltage (230).

公开(公告)号：EP1402535A1

公开(公告)日：2004-03-31

申请号：EP01274195.5

申请日：2001-11-14

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： FASTOW, Richard, M. ,  HADDAD, Sameer ,  CLEVELAND, Lee

IPC: G11C16/34

CPC classification number: G11C16/3422 ,  G11C16/344 ,  G11C16/3445

Abstract: A technique is provided for reducing column leakage in a flash EEPROM device (10) during an erase verification process, thereby preventing false verifies. The technique has application in NOR arrays or other types of arrays in which a number of cells (100) are connected in parallel. The technique operates by reducing the leakage of the unselected cells in parallel to the selected cell being verified, thereby preventing false verifies. The technique can also be used in conjunction with other techniques for reducing column leakage, such as soft programming, automatic programming disturb erase (APDE), or various other Vth compacting schemes.

公开(公告)号：EP1344221A2

公开(公告)日：2003-09-17

申请号：EP01959389.6

申请日：2001-07-31

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： AKAOGI, Takao ,  AL-SHAMMA, Ali ,  KIM, Yong ,  CLEVELAND, Lee ,  LIN, Jin-Lien ,  NGUYEN, Kendra ,  TEH, Boon Tang

IPC: G11C8/08 ,  G11C16/08

CPC classification number: G11C16/08 ,  G11C8/10

Abstract: A flash memory (100) having word line decoding and selection architecture is described. The flash memory include first (202, 204) and second (206, 208) sectors of memory cells, first (201, 212) and second (214, 216) local driver circuits, first (218), second (222, 224) and third (226, 228) decoding circuits, and a driving circuit (220). A first side of decoding circuitry (218) activates a first selected plurality of local driver circuits (210, 212) and a second side of decoding circuitry (218) activates a second selected plurality of local driver circuits (214, 216). The second decoding circuits (222, 224) are coupled to the first local driver circuit. The third decoding circuits (226, 228) are coupled to the second local driver circuits (214, 216) and supply a second boosted voltage to the second selected word line. The driving circuit (220) supplies boosted voltages to the first, second and third decoding circuites (218, 22, 224, 226, 228) and the first and second local river circuits (210, 212, 214, 216).