公开(公告)号：WO1997050112A1

公开(公告)日：1997-12-31

申请号：PCT/US1997002389

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  WRISTERS, Derick, J. ,  FULFORD, H., Jim, Jr.

IPC: H01L21/02

CPC classification number: G03F7/70466 ,  G03F7/2022 ,  G03F7/70475 ,  H01L21/0334

Abstract: A method of selectively exposing a material over a substrate is disclosed. The method includes forming a material over a semiconductor substrate, forming a photosensitive layer over the material, projecting a first image pattern onto the photosensitive layer that defines a first boundary for the material, projecting a second image pattern onto the photosensitive layer after projecting the first image pattern such that the second image pattern partially overlaps the first image pattern and defines a second boundary for the material, and removing portions of the photosensitive layer corresponding to the first and second image patterns. Preferably, the first and second image patterns are essentially identical to and laterally shifted with respect to one another. In this manner, the photosensitive layer selectively exposes the material adjacent to the first and second boundaries while covering the material between the first and second boundaries, and the distance between the first and second boundaries decreases as the overlap between the first and second image patterns decreases. Advantageously, the first and second boundaries can be closer than the minimum resolution of the photolithographic system used to pattern the photosensitive layer.

Abstract translation: 公开了一种在衬底上选择性地暴露材料的方法。 该方法包括在半导体衬底上形成材料，在材料上形成感光层，将第一图案图案投射到限定材料的第一边界的光敏层上，将第一图像图案投射到感光层上， 图像图案，使得第二图像图案部分地与第一图像图案重叠并且限定材料的第二边界，以及去除与第一和第二图像图案相对应的感光层的部分。 优选地，第一和第二图像图案基本上彼此相同并且相对于彼此横向移位。 以这种方式，感光层选择性地暴露与第一和第二边界相邻的材料，同时覆盖第一和第二边界之间的材料，并且第一和第二边界之间的距离随着第一和第二图像图案之间的重叠减小而减小 。 有利地，第一和第二边界可以比用于图案感光层的光刻系统的最小分辨率更接近。

公开(公告)号：WO1997041596A1

公开(公告)日：1997-11-06

申请号：PCT/US1997002493

申请日：1997-02-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  HAUSE, Fred, N. ,  CHANG, Kuang-Yeh

IPC: H01L21/76

CPC classification number: H01L21/3144 ,  H01L21/3185 ,  H01L21/76224 ,  Y10S148/05

Abstract: A method of forming an improved isolation trench between active regions within the semiconductor substrate. The improved method incorporates a trench liner having a nitrogen content of approximately 0.5 to 2.0 percent. A pad layer is formed on a silicon substrate and a nitride layer is formed on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into the trench liner. Incorporation of nitrogen into the trench liner can be accomplished by either forming the trench liner in the presence of a nitrogen bearing ambient or by forming a pure SiO2 trench liner and subsequently implanting the SiO2 trench liner with nitrogen. After formation of the nitrogenated trench liner, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.

Abstract translation: 一种在半导体衬底内的有源区之间形成改进的隔离沟槽的方法。 改进的方法包括氮含量为约0.5至2.0％的沟槽衬垫。 在硅衬底上形成衬垫层，并在衬垫层上形成氮化物层。 此后，在氮化硅层上图案化光致抗蚀剂层，使得随后将形成隔离沟槽的氮化物层的区域被暴露。 接下来，蚀刻掉位于氮化物层的暴露区域之下的氮化物层和焊盘层的暴露区域以暴露硅衬底的区域。 随后，用干蚀刻工艺将隔离沟槽蚀刻到硅衬底中。 然后形成沟槽衬垫，并且氮结合到沟槽衬里中。 通过在存在氮气环境的情况下形成沟槽衬垫或通过形成纯的SiO 2沟槽衬垫并随后用氮气注入SiO 2沟槽衬垫，可以将氮掺入到沟槽衬里中。 在形成氮化沟槽衬垫之后，用优选由CVD氧化物构成的电介质填充沟槽。 此后，CVD填充电介质被平坦化，并且氮化物层被剥离。

公开(公告)号：WO1996031903A1

公开(公告)日：1996-10-10

申请号：PCT/US1996002461

申请日：1996-02-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHANG, Kuang-Yeh ,  LIU, Yowjuang, William ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N.

IPC: H01L21/20

CPC classification number: H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/76294

Abstract: An oxide layer is thermally grown over a semiconductor body, and openings are etched in the oxide layer to expose portions of the surface of the semiconductor body. Then, epitaxial regions are grown from the semiconductor body into the openings in the oxide layer, which epitaxial regions will eventually become the active regions of devices.

Abstract translation: 氧化物层在半导体本体上热生长，并且在氧化物层中蚀刻开口以暴露半导体主体表面的部分。 然后，外延区域从半导体主体生长到氧化物层中的开口中，这些外延区域最终将成为器件的有源区域。

公开(公告)号：WO1996019011A1

公开(公告)日：1996-06-20

申请号：PCT/US1995015299

申请日：1995-11-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHANG, K., Y. ,  GARDNER, Mark, I. ,  HAUSE, Fred

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/823814

Abstract: A method of fabricating a MOS integrated circuit device utilizes high energy, high current implanting of ions through a layer of oxide to form heavily doped source and drain regions which are self-aligned with a polysilicon gate. A thick portion of the oxide layer adjacent to the polysilicon gate prevents heavy doping in the substrate next to the gate. The oxide layer is removed and a liightly doped drain (LDD) implant forms an LDD region which is self-aligned with the gate. Using this method the source/drain and LDD implants are performed using only a single mask and etch operation, rater than two mask and etch operations which are necessary using a conventional process.

Abstract translation: 制造MOS集成电路器件的方法利用高能量，高电流注入离子通过氧化层形成与多晶硅栅极自对准的重掺杂源极和漏极区。 与多晶硅栅极相邻的氧化物层的厚部分防止在栅极旁边的衬底中的重掺杂。 去除氧化物层，并且掺杂稀土的漏极（LDD）注入器形成与栅极自对准的LDD区域。 使用该方法，仅使用单个掩模和蚀刻操作来执行源/漏极和LDD注入，而不是使用常规工艺所必需的两个掩模和蚀刻操作。

公开(公告)号：WO1998025183A1

公开(公告)日：1998-06-11

申请号：PCT/US1997023139

申请日：1997-12-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MOORE, Bradley, T. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N. ,  MICHAEL, Mark, W. ,  WRISTERS, Derick, J.

IPC: G03F07/20

CPC classification number: G03F7/70058 ,  G03F7/70591 ,  G03F7/70891

Abstract: A method of inspecting a lens (16) includes projecting a first amount of radiation through a first test pattern (42, 44) and the lens to provide a first lens error associated with a first heating of the lens, projecting a second amount of radiation through a second test pattern (52, 54) and the lens to provide a second lens error associated with a second heating of the lens, and using the first and second lens errors to provide image displacement data that varies as a function of heating the lens. In this manner, corrections can be made for localized lens heating that is unique to a given reticle. The method is well-suited for photolithographic systems such as step and repeat systems.

Abstract translation: 检查透镜（16）的方法包括：通过第一测试图案（42,44）和透镜投射第一量的辐射，以提供与透镜的第一加热相关联的第一透镜误差，投射第二量的辐射 通过第二测试图案（52,54）和透镜提供与透镜的第二加热相关联的第二透镜误差，并且使用第一和第二透镜误差来提供作为加热透镜的函数而变化的图像位移数据 。 以这种方式，可以对给定掩模版特有的局部透镜加热进行校正。 该方法非常适合于光刻系统，如步进和重复系统。

公开(公告)号：WO1998011610A1

公开(公告)日：1998-03-19

申请号：PCT/US1997016260

申请日：1997-09-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  HAUSE, Fred, N.

IPC: H01L29/78

CPC classification number: H01L29/66621 ,  H01L29/7834 ,  Y10S257/90

Abstract: A field effect transistor comprising a semiconductor substrate (100) having a transistor trench extending downward from an upper surface of the semiconductor substrate. The trench extends to a trench depth below an upper surface of the semiconductor substrate. The transistor further includes a gate dielectric layer that is formed on floor of the transistor trench over a channel region (108) of the semiconductor substrate. A conductive gate structure (132) is formed above and in contact with the gate dielectric layer. A source/drain impurity distribution is formed within a source/drain region (140a, 140b) of the semiconductor substrate. The source/drain region is laterally disposed on either side of the channel region of the semiconductor substrate. In a preferred embodiment, the trench depth is between 100-500 nm (1000-5000 angstroms) and a thickness of the conductive gate structure is less than 500 nm (5000 angstroms) such that an upper surface of the conductive gate structure is level with or below an upper surface of the semiconductor substrate. The gate dielectric layer suitably comprises a thermal oxide having a thickness of approximately 2-20 nm (20-200 angstroms). In a lightly doped drain (LDD) embodiment, the source/drain impurity distribution includes a lightly doped region (146a, 146b) and a heavily doped region (138a, 138b). The lightly doped region extends laterally from the channel region of the transistor to the heavily doped region. In the preferred embodiment, a lateral dimension of the channel region of the transistor is approximately 100-300 nm.

Abstract translation: 一种场效应晶体管，包括具有从半导体衬底的上表面向下延伸的晶体管沟槽的半导体衬底（100）。 沟槽延伸到半导体衬底的上表面下方的沟槽深度。 晶体管还包括在半导体衬底的沟道区域（108）上形成在晶体管沟槽的底层上的栅极电介质层。 导电栅极结构（132）形成在栅极介电层的上方并与栅极电介质层接触。 在半导体衬底的源/漏区（140a，140b）内形成源/漏杂质分布。 源极/漏极区域横向地设置在半导体衬底的沟道区域的任一侧上。 在优选实施例中，沟槽深度在100-500nm（1000-5000埃）之间，并且导电栅极结构的厚度小于500nm（5000埃），使得导电栅极结构的上表面与 或者在半导体衬底的上表面之下。 栅介质层适当地包括厚度约为2-20nm（20-200埃）的热氧化物。 在轻掺杂漏极（LDD）实施例中，源极/漏极杂质分布包括轻掺杂区域（146a，146b）和重掺杂区域（138a，138b）。 轻掺杂区域从晶体管的沟道区域横向延伸到重掺杂区域。 在优选实施例中，晶体管的沟道区的横向尺寸约为100-300nm。

公开(公告)号：WO1998010470A1

公开(公告)日：1998-03-12

申请号：PCT/US1997015505

申请日：1997-09-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KADOSH, Daniel ,  GARDNER, Mark, I. ,  DAWSON, Robert

IPC: H01L29/78

CPC classification number: H01L29/66659 ,  H01L29/665 ,  H01L29/7835

Abstract: An asymmetrical IGFET including a lightly and heavily doped drain regions and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and ultra-heavily doped source region provide channel junctions. A method of making the IGFET includes providing a semiconductor substrate, forming a gate with first and second opposing sidewalls over the substrate, applying a first ion implantation to implant lightly doped source and drain regions into the substrate, applying a second ion implantation to convert substantially all of the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming a drain-side spacer adjacent to the second sidewall, and applying a third ion implantation to convert the heavily doped source region into an ultra-heavily doped source region and to convert a portion of the lightly doped drain region outside the drain-side spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the drain-side spacer. Advantageously, the IGFET has low source-drain series resistance and reduces hot carrier effects.

Abstract translation: 公开了一种包括轻掺杂和重掺杂漏极区域和超重掺杂源极区域的非对称IGFET。 优选地，轻掺杂漏极区域和超重掺杂源极区域提供通道结。 制造IGFET的方法包括提供半导体衬底，在衬底上形成具有第一和第二相对侧壁的栅极，施加第一离子注入以将轻掺杂的源极和漏极区域注入到衬底中，施加第二离子注入以基本上转换 将所有轻掺杂源区域全部掺入重掺杂源区，而不掺杂轻掺杂漏极区，形成与第二侧壁相邻的漏极侧隔离层，以及施加第三离子注入以将重掺杂源区转换成超掺杂源区， 并且将漏极侧间隔物外部的轻掺杂漏极区域的一部分转换为重掺杂漏极区域，而不将漏极侧间隔物下方的轻掺杂漏极区域的一部分掺杂。 有利地，IGFET具有低的源极 - 漏极串联电阻并且降低热载流子效应。

公开(公告)号：WO1998009325A1

公开(公告)日：1998-03-05

申请号：PCT/US1997009544

申请日：1997-06-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  KADOSH, Daniel

IPC: H01L21/762

CPC classification number: H01L21/76224

Abstract: A semiconductor process in which spacer structures are used to reduce the minimum dimension of a shallow trench isolation structure. First and second spacer support structures are formed over first and second active regions within the semiconductor substrate, respectively. Thereafter, spacer structures are formed on side walls of the spacer support structures such that a trench region of the semiconductor substrate remains exposed. If the spacer support structures are formed a lateral distance from each other approximately equal to a minimum dimension of the photolithography apparatus, then the lateral dimension of the exposed region between the spacer structures is less than the minimum resolvable feature size of the photolithography apparatus. The isolation trench can then be etched into a trench region of the semiconductor substrate between the spacer structures. Thereafter, the trench is filled with an isolation dielectric and first and second transistors are formed within the first and second active regions respectively of the semiconductor substrate.

Abstract translation: 使用间隔结构来减小浅沟槽隔离结构的最小尺寸的半导体工艺。 分别在半导体衬底内的第一和第二有源区上形成第一和第二间隔物支撑结构。 此后，在间隔件支撑结构的侧壁上形成间隔结构，使得半导体衬底的沟槽区域保持暴露。 如果间隔件支撑结构形成彼此的横向距离，近似等于光刻设备的最小尺寸，则间隔结构之间的暴露区域的横向尺寸小于光刻设备的最小可分辨特征尺寸。 然后可以将隔离沟槽蚀刻到间隔物结构之间的半导体衬底的沟槽区域中。 此后，沟槽填充有隔离电介质，并且第一和第二晶体管分别形成在半导体衬底的第一和第二有源区域内。

公开(公告)号：WO1998002918A1

公开(公告)日：1998-01-22

申请号：PCT/US1997005176

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  DUANE, Michael, P. ,  WRISTERS, Derick, J.

IPC: H01L21/336

CPC classification number: H01L29/66659 ,  H01L29/7835

Abstract: A method for fabrication of a non-symmetrical LDD-IGFET is described. In one embodiment, the method includes providing a semiconductor substrate having a gate insulator (104) and a gate electrode (106), the gate electrode having opposing first and second sidewalls (103, 105) defining the length of the gate electrode and a top surface. Lightly doped source (108) and drain (110) regions are implanted into the semiconductor substrate and are substantially aligned with the sidewalls of the gate electrode. After implanting the lightly doped regions, first and second spacers (112, 114) are formed adjacent to the first and second sidewalls of the gate electrode. After forming the spacers, a portion of the gate electrode is removed to form a third sidewall (117) of the gate electrode opposite the second sidewall (105), thereby eliminating the first sidewall and reducing the length of the gate electrode. After removing the first spacer, heavily doped source (120) and drain (118) regions are implanted into the semiconductor substrate. The heavily doped drain region is substantially aligned with the outer edge of the second spacer, a portion of the lightly doped drain regions is protected beneath the second spacer, and the heavily doped source region is substantially aligned with the third sidewall. In another embodiment, the heavily doped drain region is implanted after the spacers are formed but before the third sidewall is formed and the heavily doped source region is implanted after forming the third sidewall.

Abstract translation: 描述了一种用于制造非对称LDD-IGFET的方法。 在一个实施例中，该方法包括提供具有栅极绝缘体（104）和栅电极（106）的半导体衬底，所述栅电极具有限定栅电极的长度的相对的第一和第二侧壁（103,105） 表面。 将轻掺杂源（108）和漏极（110）区域注入到半导体衬底中并且基本上与栅电极的侧壁对准。 在注入轻掺杂区域之后，第一和第二间隔物（112,114）邻近栅电极的第一和第二侧壁形成。 在形成间隔物之后，去除栅电极的一部分以形成与第二侧壁（105）相对的栅电极的第三侧壁（117），由此消除第一侧壁并减小栅电极的长度。 在去除第一间隔物之后，将重掺杂的源极（120）和漏极（118）区域注入到半导体衬底中。 重掺杂漏极区域基本上与第二间隔物的外边缘对准，轻掺杂漏极区域的一部分被保护在第二间隔物下方，并且重掺杂源极区域基本上与第三侧壁对准。 在另一个实施例中，在形成间隔物之后但在形成第三侧壁之前注入重掺杂漏极区，并且在形成第三侧壁之后注入重掺杂源极区。

公开(公告)号：WO1998002913A2

公开(公告)日：1998-01-22

申请号：PCT/US1997005089

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  WRISTERS, Derick, J. ,  FULFORD, H., Jim

IPC: H01L21/033

CPC classification number: G03F7/70466 ,  G03F7/00 ,  H01L21/0337 ,  Y10S438/947

Abstract: A method of forming a gate electrode for an insulated-gatefield-effectransistor (IGFET) is disclosed. The method includes forming a gate material for providing a gate electrode over a semiconductor substrate, forming a first mask over the gate material wherein the first mask includes an opening that defines a first edge of the gate electrode, removing a first portion of the gate material to form the first edge of the gate electrode as defined by the first mask, forming a second mask over the gate material after removing the first mask wherein the second mask includes an opening that defines a second edge of the gate electrode, removing a second portion of the gate material to form the second edge of the gate electrode as defined by the second mask, and removing the second mask. Thus, the gate electrode is defined by a lateral displacement between the openings in the first and second masks. Preferably, the first and second masks are photoresist, and the length between the first and second edges of the gate electrode is less than the minimum resolution of a photolithographic system used to pattern the masks.

Abstract translation: 公开了一种形成绝缘栅场效应晶体管（IGFET）的栅电极的方法。 该方法包括形成用于在半导体衬底上提供栅电极的栅极材料，在栅极材料上形成第一掩模，其中第一掩模包括限定栅电极的第一边缘的开口，去除栅极材料的第一部分 以形成由第一掩模限定的栅电极的第一边缘，在去除第一掩模之后在栅极材料上形成第二掩模，其中第二掩模包括限定栅电极的第二边缘的开口，去除第二部分 以形成由第二掩模限定的栅电极的第二边缘，并且移除第二掩模。 因此，栅电极由第一和第二掩模中的开口之间的横向位移限定。 优选地，第一和第二掩模是光致抗蚀剂，并且栅电极的第一和第二边缘之间的长度小于用于对掩模进行图案化的光刻系统的最小分辨率。