公开(公告)号：WO2003054951A1

公开(公告)日：2003-07-03

申请号：PCT/US2002/041103

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： LUNING, Scott ,  KADOSH, Daniel ,  CHEEK, Jon, D. ,  BULLER, James, F.

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/2652

Abstract: A method of forming a semiconductor device provides a gate electrode (32) on a substrate (30); and an oxide liner (34) that is less than 100 A in thickness on the substrate (30) and the gate electrode (32). A nitride layer (38) is formed on the oxide liner (34). The nitride layer (38) is etched to form nitride spacers (40), the etching stopping on the oxide liner (34). The thinner oxide liner (34), e.g., less than 100 A, prevents the liner (34) from acting as a sink for dopants during thermal processing so that the dopants in the source/drain extension regions (36) and the source/drain regions (42) remain in the substrate (30) during the thermal processing, thereby preventing degradation of transistor performance.

Abstract translation: 形成半导体器件的方法在衬底（30）上提供栅电极（32）; 以及在所述基板（30）和所述栅电极（32）上的厚度小于100A的氧化物衬垫（34）。 在氧化物衬垫（34）上形成氮化物层（38）。 蚀刻氮化物层（38）以形成氮化物间隔物（40），蚀刻停止在氧化物衬垫（34）上。 较薄的氧化物衬垫（34）（例如小于100A）可防止衬垫（34）在热处理期间充当掺杂剂的沉陷，使得源极/漏极延伸区域（36）和源极/漏极 在热处理期间，区域（42）保留在基板（30）中，从而防止晶体管性能的劣化。

公开(公告)号：WO2004040624A2

公开(公告)日：2004-05-13

申请号：PCT/US2003/035435

申请日：2003-10-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KADOSH, Daniel

IPC: H01L21/00

CPC classification number: G05B19/41875 ,  G05B2219/32097 ,  G05B2219/32198 ,  G05B2219/32364 ,  G05B2219/45031 ,  Y02P80/40 ,  Y02P90/22 ,  Y02P90/26

Abstract: A method includes processing a workpiece in a manufacturing system (10) including a plurality of tools (30). Workpiece fabrication data related to the processing is retrieved. Future processing in the manufacturing system (10) is simulated based on the workpiece fabrication data. At least one process parameter for the future processing is predicted based on the simulating. The workpiece is processed in at least one of the tools (30) based on the predicted process parameter. A system (10) includes a plurality of tools (30) configured to process a workpiece and a simulation unit (110). The simulation unit (110) is configured to retrieve workpiece fabrication data related to the processing, simulate future processing for the workpiece based on the workpiece fabrication data, and predict at least one process parameter for the future processing based on the simulating, wherein at least one of the tools (30) is configured to process the workpiece based on the predicted process parameter.

Abstract translation: 一种方法包括在包括多个工具（30）的制造系统（10）中处理工件。 检索与处理相关的工件制造数据。 基于工件制造数据模拟制造系统（10）中的未来加工。 基于模拟预测未来处理的至少一个过程参数。 基于预测的工艺参数在至少一个工具（30）中处理工件。 系统（10）包括被配置为处理工件和模拟单元（110）的多个工具（30）。 仿真单元（110）被配置为检索与该处理相关的工件制造数据，基于工件制造数据模拟工件的未来处理，并且基于模拟预测用于将来处理的至少一个工艺参数，其中至少 工具（30）中的一个被配置为基于预测的过程参数来处理工件。

公开(公告)号：WO2003054952A1

公开(公告)日：2003-07-03

申请号：PCT/US2002/041331

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BULLER, James, F. ,  WU, David ,  LUNING, Scott ,  WRISTERS, Derick, J. ,  KADOSH, Daniel

IPC: H01L21/336

CPC classification number: H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

Abstract: Semiconductor devices with improved transistor performance are fabricated by forming a composite oxide/nitride liner (24,25) under a gate electrode sidewall spacer (40). Embodiements include depositing a conformal oxide layer (24) by decoupled plasma deposition, depositing a conformal nitride layer (25) by decoupled plasma deposition, depositing a spacer layer (30) and then etching.

Abstract translation: 具有改善的晶体管性能的半导体器件通过在栅电极侧壁间隔物（40）下形成复合氧化物/氮化物衬垫（24,25）来制造。 实例包括通过解耦等离子体沉积沉积保形氧化物层（24），通过解耦等离子体沉积沉积共形氮化物层（25），沉积间隔层（30）然后蚀刻。

公开(公告)号：WO1998010470A1

公开(公告)日：1998-03-12

申请号：PCT/US1997015505

申请日：1997-09-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KADOSH, Daniel ,  GARDNER, Mark, I. ,  DAWSON, Robert

IPC: H01L29/78

CPC classification number: H01L29/66659 ,  H01L29/665 ,  H01L29/7835

Abstract: An asymmetrical IGFET including a lightly and heavily doped drain regions and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and ultra-heavily doped source region provide channel junctions. A method of making the IGFET includes providing a semiconductor substrate, forming a gate with first and second opposing sidewalls over the substrate, applying a first ion implantation to implant lightly doped source and drain regions into the substrate, applying a second ion implantation to convert substantially all of the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming a drain-side spacer adjacent to the second sidewall, and applying a third ion implantation to convert the heavily doped source region into an ultra-heavily doped source region and to convert a portion of the lightly doped drain region outside the drain-side spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the drain-side spacer. Advantageously, the IGFET has low source-drain series resistance and reduces hot carrier effects.

Abstract translation: 公开了一种包括轻掺杂和重掺杂漏极区域和超重掺杂源极区域的非对称IGFET。 优选地，轻掺杂漏极区域和超重掺杂源极区域提供通道结。 制造IGFET的方法包括提供半导体衬底，在衬底上形成具有第一和第二相对侧壁的栅极，施加第一离子注入以将轻掺杂的源极和漏极区域注入到衬底中，施加第二离子注入以基本上转换 将所有轻掺杂源区域全部掺入重掺杂源区，而不掺杂轻掺杂漏极区，形成与第二侧壁相邻的漏极侧隔离层，以及施加第三离子注入以将重掺杂源区转换成超掺杂源区， 并且将漏极侧间隔物外部的轻掺杂漏极区域的一部分转换为重掺杂漏极区域，而不将漏极侧间隔物下方的轻掺杂漏极区域的一部分掺杂。 有利地，IGFET具有低的源极 - 漏极串联电阻并且降低热载流子效应。

公开(公告)号：WO1998009325A1

公开(公告)日：1998-03-05

申请号：PCT/US1997009544

申请日：1997-06-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  KADOSH, Daniel

IPC: H01L21/762

CPC classification number: H01L21/76224

Abstract: A semiconductor process in which spacer structures are used to reduce the minimum dimension of a shallow trench isolation structure. First and second spacer support structures are formed over first and second active regions within the semiconductor substrate, respectively. Thereafter, spacer structures are formed on side walls of the spacer support structures such that a trench region of the semiconductor substrate remains exposed. If the spacer support structures are formed a lateral distance from each other approximately equal to a minimum dimension of the photolithography apparatus, then the lateral dimension of the exposed region between the spacer structures is less than the minimum resolvable feature size of the photolithography apparatus. The isolation trench can then be etched into a trench region of the semiconductor substrate between the spacer structures. Thereafter, the trench is filled with an isolation dielectric and first and second transistors are formed within the first and second active regions respectively of the semiconductor substrate.

Abstract translation: 使用间隔结构来减小浅沟槽隔离结构的最小尺寸的半导体工艺。 分别在半导体衬底内的第一和第二有源区上形成第一和第二间隔物支撑结构。 此后，在间隔件支撑结构的侧壁上形成间隔结构，使得半导体衬底的沟槽区域保持暴露。 如果间隔件支撑结构形成彼此的横向距离，近似等于光刻设备的最小尺寸，则间隔结构之间的暴露区域的横向尺寸小于光刻设备的最小可分辨特征尺寸。 然后可以将隔离沟槽蚀刻到间隔物结构之间的半导体衬底的沟槽区域中。 此后，沟槽填充有隔离电介质，并且第一和第二晶体管分别形成在半导体衬底的第一和第二有源区域内。

公开(公告)号：EP1456877B1

公开(公告)日：2010-07-21

申请号：EP02796042.6

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BULLER, James, F. ,  WU, David ,  LUNING, Scott ,  WRISTERS, Derick, J. ,  KADOSH, Daniel

IPC: H01L21/336 ,  H01L29/49

CPC classification number: H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

公开(公告)号：EP0938752A1

公开(公告)日：1999-09-01

申请号：EP97939764.0

申请日：1997-09-03

Applicant: Advanced Micro Devices, Inc.

Inventor： KADOSH, Daniel ,  GARDNER, Mark, I. ,  DAWSON, Robert

IPC: H01L21 ,  H01L29

CPC classification number: H01L29/66659 ,  H01L29/665 ,  H01L29/7835

Abstract: An asymmetrical IGFET including a lightly and heavily doped drain regions and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and ultra-heavily doped source region provide channel junctions. A method of making the IGFET includes providing a semiconductor substrate, forming a gate with first and second opposing sidewalls over the substrate, applying a first ion implantation to implant lightly doped source and drain regions into the substrate, applying a second ion implantation to convert substantially all of the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming a drain-side spacer adjacent to the second sidewall, and applying a third ion implantation to convert the heavily doped source region into an ultra-heavily doped source region and to convert a portion of the lightly doped drain region outside the drain-side spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the drain-side spacer. Advantageously, the IGFET has low source-drain series resistance and reduces hot carrier effects.

公开(公告)号：EP1010200A1

公开(公告)日：2000-06-21

申请号：EP98923905.8

申请日：1998-06-03

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： GARDNER, Mark, I. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  HAUSE, Frederick, N. ,  KADOSH, Daniel ,  MICHAEL, Mark, W. ,  MOORE, Bradley, T. ,  WRISTERS, Derick, J.

IPC: H01L21/336 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/823814 ,  H01L29/1033 ,  H01L29/518 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7833

Abstract: A nitrogen implanted region formed substantially below and substantially adjacent to a source/drain region of an IGFET forms a liner to retard the diffusion of the source/drain dopant atoms during a subsequent heat treatment operation such as an annealing step. The nitrogen liner may be formed by implantation of nitrogen to a given depth before the implantation of source/drain dopant to a lesser depth. Nitrogen may also be introduced into regions of the IGFET channel region beneath the gate electrode for retarding subsequent lateral diffusion of the source/drain dopant. Such nitrogen introduction may be accomplished using one or more angled implantation steps, or may be accomplished by annealing an implanted nitrogen layer formed using a perpendicular implant aligned to the gate electrode. The liner may be formed on the drain side of the IGFET or on both source and drain side, and may be formed under a lightly-doped region or under a heavily-doped region of the drain and/or source. Such a liner is particularly advantageous for boron-doped source/drain regions, and may be combined with N-channel IGFETs formed without such liners.

公开(公告)号：EP1556802A2

公开(公告)日：2005-07-27

申请号：EP03778141.6

申请日：2003-10-27

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： KADOSH, Daniel

IPC: G06F17/50

CPC classification number: G05B19/41875 ,  G05B2219/32097 ,  G05B2219/32198 ,  G05B2219/32364 ,  G05B2219/45031 ,  Y02P80/40 ,  Y02P90/22 ,  Y02P90/26

Abstract: A method includes processing a workpiece in a manufacturing system (10) including a plurality of tools (30). Workpiece fabrication data related to the processing is retrieved. Future processing in the manufacturing system (10) is simulated based on the workpiece fabrication data. At least one process parameter for the future processing is predicted based on the simulating. The workpiece is processed in at least one of the tools (30) based on the predicted process parameter. A system (10) includes a plurality of tools (30) configured to process a workpiece and a simulation unit (110). The simulation unit (110) is configured to retrieve workpiece fabrication data related to the processing, simulate future processing for the workpiece based on the workpiece fabrication data, and predict at least one process parameter for the future processing based on the simulating, wherein at least one of the tools (30) is configured to process the workpiece based on the predicted process parameter.

公开(公告)号：EP1456877A1

公开(公告)日：2004-09-15

申请号：EP02796042.6

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： BULLER, James, F. ,  WU, David ,  LUNING, Scott ,  WRISTERS, Derick, J. ,  KADOSH, Daniel

IPC: H01L21/336

CPC classification number: H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

Abstract: Semiconductor devices with improved transistor performance are fabricated by forming a composite oxide/nitride liner (24,25) under a gate electrode sidewall spacer (40). Embodiements include depositing a conformal oxide layer (24) by decoupled plasma deposition, depositing a conformal nitride layer (25) by decoupled plasma deposition, depositing a spacer layer (30) and then etching.