CONTROL TECHNIQUES FOR MOTOR DRIVEN SYSTEMS
    12.
    发明申请

    公开(公告)号:WO2010090904A2

    公开(公告)日:2010-08-12

    申请号:PCT/US2010022083

    申请日:2010-01-26

    CPC classification number: H02P25/034

    Abstract: Embodiments of the present invention provide a motor-driven mechanical system with a detection system to measure properties of a back channel and derive oscillatory characteristics of the mechanical system. Uses of the detection system may include calculating the resonant frequency of the mechanical system and a threshold drive DTH required to move the mechanical system from the starting mechanical stop position. System manufacturers often do not know the resonant frequency and DTH of their mechanical systems precisely. Therefore, the calculation of the specific mechanical system's resonant frequency and DTH rather than depending on the manufacturer's expected values improves precision in the mechanical system use. The backchannel calculations may be used either to replace or to improve corresponding pre-programmed values.

    NO-MISSING-CODE ANALOG TO DIGITAL CONVERTER SYSTEM AND METHOD
    13.
    发明申请
    NO-MISSING-CODE ANALOG TO DIGITAL CONVERTER SYSTEM AND METHOD 审中-公开
    数字转换器系统和方法的失效代码模拟

    公开(公告)号:WO2007126614A3

    公开(公告)日:2009-02-05

    申请号:PCT/US2007006783

    申请日:2007-03-19

    CPC classification number: H03M1/0641 H03M1/0626 H03M1/12

    Abstract: A no-missing-code output from a SAR, pipeline, folding, flash analog to digital conversion can be obtained by providing an analog input to an analog to digital converter having a predetermined m bit resolution output and a predetermined missing code capability and generating in a digital filter from the m bit output and the dither of the random noise components of the m_bit output n bit output and greater than the predetermined missing code capability of the analog to digital converter.

    Abstract translation: 通过向具有预定的m位分辨率输出和预定的缺失代码能力的模数转换器提供模拟输入,可以获得来自SAR,流水线,折叠,闪存模数转换的无丢失代码输出 来自m位输出的数字滤波器和m_bit输出n位输出的随机噪声分量的抖动,并且大于模数转换器的预定缺失代码能力。

    CONTROL TECHNIQUES FOR MOTOR DRIVEN SYSTEMS
    14.
    发明申请
    CONTROL TECHNIQUES FOR MOTOR DRIVEN SYSTEMS 审中-公开
    电机驱动系统的控制技术

    公开(公告)号:WO2010090910A3

    公开(公告)日:2012-01-19

    申请号:PCT/US2010022117

    申请日:2010-01-26

    CPC classification number: H02P25/034

    Abstract: Embodiments of the present invention provide a motor-driven mechanical system with a detection system to measure properties of a back channel and derive oscillatory characteristics of the mechanical system. Uses of the detection system may include calculating the resonant frequency of the mechanical system and a threshold drive DTH required to move the mechanical system from the starting mechanical stop position. System manufacturers often do not know the resonant frequency and DTH of their mechanical systems precisely. Therefore, the calculation of the specific mechanical system's resonant frequency and DTH rather than depending on the manufacturer's expected values improves precision in the mechanical system use. The backchannel calculations may be used either to replace or to improve corresponding pre-programmed values.

    Abstract translation: 本发明的实施例提供一种具有检测系统的电机驱动机械系统,用于测量后通道的性质并导出机械系统的振荡特性。 检测系统的使用可以包括计算机械系统的谐振频率和将机械系统从起动机械停止位置移动所需的阈值驱动DTH。 系统制造商往往不了解其机械系统的谐振频率和DTH。 因此,特定机械系统的谐振频率和DTH的计算而不是依赖于制造商的预期值来提高机械系统使用的精度。 反向通道计算可用于替换或改善相应的预编程值。

    IMPROVED CHARGE PUMP SYSTEM FOR FAST LOCKING PHASE LOCK LOOP
    15.
    发明申请
    IMPROVED CHARGE PUMP SYSTEM FOR FAST LOCKING PHASE LOCK LOOP 审中-公开
    改进的电荷泵系统用于快速锁定锁相环

    公开(公告)号:WO2005004332A3

    公开(公告)日:2005-05-26

    申请号:PCT/US2004020550

    申请日:2004-06-25

    CPC classification number: H03K3/0231 H03L7/0896

    Abstract: A charge pump system for a fast locking phase lock loop includes a set n of charge pump units; and a control logic circuit for enabling the set of n charge pump units to produce up and down charge pulses with a nominal charge pump mismatch in a wide bandwidth mode; and in a narrow bandwidth mode enabling at least a subset of the n charge pump units sequentially to produce an average charge pump mismatch in narrow bandwidth mode that matches the nominal charge pump mismatch in the wide bandwidth mode.

    Abstract translation: 用于快速锁定锁相环的电荷泵系统包括一组电荷泵单元; 以及控制逻辑电路,用于使该组n个电荷泵单元在宽带宽模式下产生具有标称电荷泵失配的上和下充电脉冲; 并且在窄带宽模式下,使得n个电荷泵单元的至少一个子集顺序地产生与宽带宽模式下的标称电荷泵失配相匹配的窄带宽模式下的平均电荷泵失配。

    GAIN COMPENSATED FRACTIONAL-N PHASE LOCK LOOP SYSTEM AND METHOD
    16.
    发明申请
    GAIN COMPENSATED FRACTIONAL-N PHASE LOCK LOOP SYSTEM AND METHOD 审中-公开
    增益补偿相位锁相环系统及方法

    公开(公告)号:WO2005004333A2

    公开(公告)日:2005-01-13

    申请号:PCT/US2004020551

    申请日:2004-06-25

    CPC classification number: H03K3/0231 H03L7/0896

    Abstract: A gain compensation technique for a fractional-N phase lock loop includes locking a reference signal with the N divider feedback signal in a phase lock loop including a phase detector, charge pump, loop filter and voltage control oscillator with an N divider in its feedback loop; driving the N divider with a sigma delta modulator including at least one integrator to obtain a predetermined fractional-N feedback signal; and commanding a scaling in phase lock loop gain by a predetermined factor and synchronously inversely scaling by that factor the contents of at least one of the integrators.

    Abstract translation: 用于分数N相位锁相环的增益补偿技术包括:将N分频器反馈信号的参考信号锁定在包括相位检测器,电荷泵,环路滤波器和压控振荡器的锁相环中,在其反馈环路中使用N分频器 ; 用包括至少一个积分器的Σ-Δ调制器驱动N分频器以获得预定的分数N反馈信号; 并且通过预定因子来指令锁相环增益的缩放,并且通过所述因子对至少一个积分器的内容进行同步反比。

    FRACTIONAL-N SYNTHESISER AND METHOD OF SYNCHRONISATION OF THE OUTPUT PHASE
    19.
    发明公开
    FRACTIONAL-N SYNTHESISER AND METHOD OF SYNCHRONISATION OF THE OUTPUT PHASE 有权
    FRAKTIONAL-N-SYNTHESIZER UND VERFAHREN ZUR SYNCHRONIZATION DER AUSGANGSPHASE

    公开(公告)号:EP1391043A4

    公开(公告)日:2004-09-29

    申请号:EP02739834

    申请日:2002-05-17

    CPC classification number: H03L7/1976 G06F7/68

    Abstract: A fractional-N synthesiser (10) and method of phase synchronising the output signal with the input reference signal in a fractional-N synthesiser by generating a synchronisation pulse at integer multiples of periods of he input reference signal (28) and gating (44) the synchronisation pulse to re-initialise the interpolator (26) in the fractional-N synthesiser to synchronise the phase of the output signal with the input reference signal.

    Abstract translation: 通过在输入参考信号(28)和选通(44)的整数倍周期处产生同步脉冲,在分数N合成器中使输出信号与输入参考信号相位同步的分数N合成器(10) 同步脉冲重新初始化分数N合成器中的内插器(26),以使输出信号的相位与输入参考信号同步。

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