公开(公告)号：AU2011261655A1

公开(公告)日：2012-10-11

申请号：AU2011261655

申请日：2011-05-26

Applicant: APPLE INC

Inventor： LILLY BRIAN P ,  KASSOFF JASON M ,  CHEN HAO

IPC: G06F13/16

Abstract: In an embodiment, a system includes a memory controller, processors and corresponding caches. The system may include sources of uncertainty that prevent the precise scheduling of data forwarding for a load operation that misses in the processor caches. The memory controller may provide an early response that indicates that data should be provided in a subsequent clock cycle. An interface unit between the memory controller and the caches/processors may predict a delay from a currently-received early response to the corresponding data, and may speculatively prepare to forward the data assuming that it will be available as predicted. The interface unit may monitor the delays between the early response and the forwarding of the data, or at least the portion of the delay that may vary. Based on the measured delays, the interface unit may modify the subsequently predicted delays.

公开(公告)号：GB2483763A

公开(公告)日：2012-03-21

申请号：GB201115481

申请日：2011-09-08

Applicant: APPLE INC

Inventor： BISWAS SUKALPA ,  CHEN HAO ,  WADHAWAN RUCHI

IPC: G06F13/16

Abstract: A memory controller 40 has several source ports 44 and several memory ports 42. Each source port receives memory operations of a particular type. The operations may be real time operations from a real time peripheral 22 or non-real time operations from a processor 14. The memory operations have quality of service parameters, which the memory controller takes into account when switching the operations. The quality of service parameters may be different for the real time and non-real time operations. When a higher quality of service is requested for an operation, previous operations from the same source may be processed with the higher quality of service. When the operations are placed into queues for the memory ports, the operations for a particular channel may be reordered based on the requested quality of service. The operations may also be sorted based on efficiency or into separate read and write queues.

公开(公告)号：NL2007411A

公开(公告)日：2012-03-19

申请号：NL2007411

申请日：2011-09-14

Applicant: APPLE INC

Inventor： BISWAS SUKALPA ,  CHEN HAO ,  WADHAWAN RUCHI

IPC: G06F12/00 ,  G06F13/18

Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

公开(公告)号：DE112014000938T5

公开(公告)日：2015-11-26

申请号：DE112014000938

申请日：2014-02-12

Applicant: APPLE INC

Inventor： HOLLAND PETER F ,  CHEN HAO ,  KUO ALBERT

IPC: G06F1/32 ,  G06T3/40

Abstract: Verfahren bezüglich der Energieverwaltung in einer Anzeige-Pipeline (200) werden offenbart. Der Anzeigezwischenspeicher (114) empfängt Bilddaten (202) über eine Datenübertragungskopplung. Eine Datenübertragungskopplung wird basierend auf der Anzeige-Pipeline (200), die in einem Skaliermodus oder einem Nicht-Skaliermodus betrieben wird, heruntergefahren. Der Anzeigezwischenspeicher (114) übertragt mindestens einen Teil der Bilddaten auf eine oder mehrere Komponenten der Anzeige-Pipeline (200), und als Reaktion auf das Übertragen wird die Datenübertragungskopplung hochgefahren. In einigen Ausführungsformen beinhaltet der Anzeigezwischenspeicher (114) eine Vielzahl von Zeilenzwischenspeichern (310a bis x), die jeweils konfiguriert sind, um eine einzelne Bildquellzeile (312) zu speichern. In einer solchen Ausführungsform beinhaltet eine Anzeige-Pipeline (200), die konfiguriert ist, um anzuzeigende Bilder zu rendern, den Anzeigezwischenspeicher (114), und das Herunterfahren erfolgt als Reaktion auf die empfangenen Bilddaten, die zwei oder mehrere Bildquellzeilen (312) enthalten.

公开(公告)号：AU2011302452B2

公开(公告)日：2014-09-04

申请号：AU2011302452

申请日：2011-08-31

Applicant: APPLE INC

Inventor： BISWAS SUKALPA ,  CHEN HAO ,  WADHAWAN RUCHI

IPC: G06F13/00

Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

公开(公告)号：AU2011261655B2

公开(公告)日：2013-12-19

申请号：AU2011261655

申请日：2011-05-26

Applicant: APPLE INC

Inventor： LILLY BRIAN P ,  KASSOFF JASON M ,  CHEN HAO

IPC: G06F13/16

Abstract: In an embodiment, a system includes a memory controller, processors and corresponding caches. The system may include sources of uncertainty that prevent the precise scheduling of data forwarding for a load operation that misses in the processor caches. The memory controller may provide an early response that indicates that data should be provided in a subsequent clock cycle. An interface unit between the memory controller and the caches/processors may predict a delay from a currently-received early response to the corresponding data, and may speculatively prepare to forward the data assuming that it will be available as predicted. The interface unit may monitor the delays between the early response and the forwarding of the data, or at least the portion of the delay that may vary. Based on the measured delays, the interface unit may modify the subsequently predicted delays.

公开(公告)号：AU2011302452A1

公开(公告)日：2013-03-28

申请号：AU2011302452

申请日：2011-08-31

Applicant: APPLE INC

Inventor： BISWAS SUKALPA ,  CHEN HAO ,  WADHAWAN RUCHI

IPC: G06F13/00

Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

公开(公告)号：DE112014000938B4

公开(公告)日：2020-06-25

申请号：DE112014000938

申请日：2014-02-12

Applicant: APPLE INC

Inventor： HOLLAND PETER F ,  CHEN HAO ,  KUO ALBERT

IPC: G06F1/32 ,  G06T3/40

Abstract: Verfahren, umfassend:Betreiben einer Anzeigeeinheit (110) in einem ersten Betriebsmodus einschließend:Empfangen, von Bilddatensätzen über eine Datenübertragungskopplung (102) durch einen Anzeigezwischenspeicher (114, 115), wobei jeder Satz eine erste Größe besitzt;Skalieren von Bilddaten von dem Anzeigezwischenspeicher (114, 115) in mindestens zwei Dimensionen durch eine Skalierungsschaltung (210, 211); undBetreiben der Anzeigeeinheit (110) in einem zweiten Betriebsmodus einschließend:Empfangen von Bilddatensätzen über die Datenübertragungskopplung (102) durch den Anzeigezwischenspeicher (114, 115), wobei jeder Satz eine zweite Größe besitzt, die größer als die erste Größe ist;Skalieren von Bilddaten vom Anzeigezwischenspeicher (114, 115) in höchstens einer Dimension durch die Skalierungsschaltung (210, 211); undHerunterfahren der Datenübertragungskopplung (102) während einem oder mehreren Zeitintervallen zwischen dem Empfangen der Bilddatensätze durch den Anzeigezwischenspeicher (114, 115).

公开(公告)号：BR102012022563A2

公开(公告)日：2015-06-09

申请号：BR102012022563

申请日：2012-09-06

Applicant: APPLE INC

Inventor： CHEN HAO ,  NOTANI RAKESH L ,  BISWAS SUKALPA

IPC: G06F13/14

Abstract: Detecção de validação de dados dinâmica.técnicas estão descritas relativas à determinação quando um sinal de validação de dados é válido para capturar os dados. Em uma modalidade, um aparelho está descrito que inclui um circuito de interface de memória configurado para determinar um valor de tempo inicial para capturar os dados de uma memória com base em um sinal de validação de dados. Em algumas modalidades, o circuito de interface de memória pode determinar este valor de tempo inicial lendo um valor conhecido da memória. Em uma modalidade, o circuito de interface de memória está ainda configurado para determinar um valor de tempo ajustado para capturar os dados, onde o circuito de interface de memória está configurado para determinar o valor de tempo ajustado utilizando o valor de tempo inicial para amostrar o sinal de validação de dados.

公开(公告)号：MX2012011336A

公开(公告)日：2012-11-30

申请号：MX2012011336

申请日：2011-05-26

Applicant: APPLE INC

Inventor： LILLY BRIAN P ,  KASSOFF JASON M ,  CHEN HAO

IPC: G06F13/16

Abstract: En una modalidad, un sistema incluye un controlador de memoria, procesadores y memorias caché correspondientes. El sistema puede incluir fuentes de incertidumbre que previenen la programación precisa de reenvío de datos para operación de carga que falla en las memoria caché del procesador. El controlador de memoria puede proporcionar una pronta respuesta que indica que los datos deben proporcionarse en un ciclo de temporizador subsecuente. Una unidad de interfase entre el controlador de memoria y los procesadores/memorias caché pueden pronosticar un retraso de una pronta respuesta actualmente recibida para los datos correspondientes, y puede preparar especulativamente el reenvío de datos asumiendo que estará disponible como se pronosticó. La unidad de interfase puede monitorizar los retrasos entre la pronta respuesta y el reenvío de los datos, o al menos la porción de retraso que puede variar. En base a los retrasos medidos, la unidad de interfase puede modificar los retrasos pronosticados subsecuentemente.