公开(公告)号：US20170317588A1

公开(公告)日：2017-11-02

申请号：US15489798

申请日：2017-04-18

Applicant: Apple Inc.

Inventor： Shawn Searles ,  Vidhya Ramachandran

IPC: H02M3/158 ,  H01L25/065 ,  H01L27/108

Abstract: A system that includes multiple integrated circuits is disclosed. A first integrated circuit of the system includes a plurality of circuit blocks, and a first circuit block of the plurality of circuit blocks includes a first power terminal. A second integrated circuit of the system includes multiple voltage regulation circuits, a second power terminal coupled to an output of a given voltage regulation circuit, and a third power terminal coupled to an input of the given voltage regulation circuit. A substrate, included in the system, includes a plurality of conductive paths, each of which includes a plurality of wires fabricated on a plurality of conductive layers. The system further includes a power management unit that may be configured to generate a power supply voltage at a fourth power terminal that is coupled to the third power terminal via a first conductive path of the plurality of conductive paths.

公开(公告)号：US20250112154A1

公开(公告)日：2025-04-03

申请号：US18643907

申请日：2024-04-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Antonietta Oliva ,  Sambasivan Narayan ,  Jun Zhai ,  Vidhya Ramachandran ,  Kamal Sikka

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/367 ,  H01L23/427 ,  H01L23/473 ,  H01L23/48 ,  H01L23/522

Abstract: Chip structures and electronic modules including a power delivery network (PDN) routing structure and signal routing structure to balance power, signaling, and thermal requirements are described. In an embodiment, the chip includes a device layer, a PDN routing structure on top of the device layer, and a signal routing structure underneath the device layer.

公开(公告)号：US20240243012A1

公开(公告)日：2024-07-18

申请号：US18622588

申请日：2024-03-29

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L21/66 ,  H01L23/00 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L21/77 ,  H01L22/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18 ,  H01L24/17 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/24195 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Systems including voltage regulator circuits are disclosed. In one embodiment, an apparatus includes a voltage regulator controller integrated circuit (IC) die including one or more portions of a voltage regulator circuit. The apparatus further includes a capacitor die, an inductor die, and an interconnect layer arranged over the voltage regulator controller IC die, the capacitor die and the inductor die. The interconnect provides electrical connections between the voltage regulator controller IC die, the capacitor die and the inductor die to form the voltage regulator circuit. In a further embodiment, the voltage regulator controller IC die, the capacitor die and the inductor die are arranged in a planar fashion within a voltage regulator module. In still another embodiment, a system IC is coupled to the voltage regulator module and includes one or more functional circuit blocks coupled to receive a regulated supply voltage generated by the voltage regulator circuit.

公开(公告)号：US20230335440A1

公开(公告)日：2023-10-19

申请号：US18307554

申请日：2023-04-26

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L25/16 ,  H01L25/03 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L21/77 ,  H01L25/16 ,  H01L25/03 ,  H01L25/18 ,  H01L22/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/17 ,  H01L2924/1427 ,  H01L2924/1436 ,  H01L2924/19042 ,  H01L2924/1432 ,  H01L2924/19103 ,  H01L2224/12105 ,  H01L2224/1703 ,  H01L2924/19104 ,  H01L2224/16265 ,  H01L2924/15192 ,  H01L2224/16235 ,  H01L2924/19041 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2924/1433 ,  H01L2924/18162 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/17181 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

公开(公告)号：US11670548B2

公开(公告)日：2023-06-06

申请号：US17080609

申请日：2020-10-26

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L25/16 ,  H01L25/03 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L21/77 ,  H01L22/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18 ,  H01L24/17 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/24195 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

公开(公告)号：US10756622B2

公开(公告)日：2020-08-25

申请号：US16231904

申请日：2018-12-24

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Jun Zhai ,  Ralf M. Schmitt ,  Vidhya Ramachandran ,  Wenjie Mao

IPC: H02M3/07 ,  G05F3/10 ,  H01L29/66 ,  H01L23/00 ,  H01L23/522

Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

公开(公告)号：US09548288B1

公开(公告)日：2017-01-17

申请号：US14966482

申请日：2015-12-11

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Chonghua Zhong ,  Shawn Searles ,  Jun Zhai ,  Young Doo Jeon ,  Huabo Chen

IPC: H01L25/16 ,  H01L23/528 ,  H01L23/50 ,  H01L21/78 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L25/16 ,  H01L21/768 ,  H01L21/78 ,  H01L23/50 ,  H01L23/528 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/16265 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1427 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/145 ,  H01L2924/14511 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2224/81

Abstract: A system that includes an integrated circuit die and a power supply decoupling unit is disclosed. The system includes an integrated circuit die, and interconnection region, and a decoupling unit. The integrated circuit die includes a plurality of circuits, which each include multiple devices interconnected using wires fabricated on a first plurality of conductive layers. The interconnection region includes multiple solder balls, and multiple conductive paths, each of which includes wires fabricated on a second plurality conductive layers. At least one solder ball is connected to an Input/Output terminal of a first circuit of the plurality of circuits via one of the conductive paths. The decoupling unit may include a plurality of capacitors and a plurality of terminals. Each terminal of the decoupling unit may be coupled to a respective power terminal of a second circuit of the plurality of circuits via the conductive paths.

Abstract translation: 公开了一种包括集成电路管芯和电源去耦单元的系统。 该系统包括集成电路管芯和互连区域以及去耦单元。 集成电路管芯包括多个电路，每个电路包括使用在第一多个导电层上制造的导线互连的多个器件。 互连区域包括多个焊球，以及多个导电路径，每个导电路径包括制造在第二多个导电层上的导线。 至少一个焊球通过导电路径之一连接到多个电路中的第一电路的输入/输出端子。 去耦单元可以包括多个电容器和多个端子。 去耦单元的每个端子可以经由导电路径耦合到多个电路中的第二电路的相应电源端子。

公开(公告)号：US20240421013A1

公开(公告)日：2024-12-19

申请号：US18585834

申请日：2024-02-23

Applicant: Apple Inc.

Inventor： Jixuan Gong ,  Vidhya Ramachandran ,  Jie-Hua Zhao ,  Young Doo Jeon ,  Wei Chen ,  Jun Zhai

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L23/58

Abstract: Integrated circuit (IC) structure, IC die structures and methods of fabrication are described in which one or more edge recesses are formed in an IC die. Upon direct bonding to an electronic component, a molding compound can be applied to the bonded structure where the molding compound fills the one or more edge recesses and encroached underneath the IC die and between the IC die and the electronic component.

公开(公告)号：US20240088032A1

公开(公告)日：2024-03-14

申请号：US17932182

申请日：2022-09-14

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Chi Nung Ni ,  Chueh-An Hsieh ,  Rekha Govindaraj ,  Jun Zhai ,  Long Huang ,  Rohan U. Mandrekar ,  Saumya K. Gandhi ,  Zhuo Yan ,  Yizhang Yang ,  Saurabh P. Sinha ,  Antonietta Oliva

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5283 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/16 ,  H01L28/40 ,  H01L2224/08265 ,  H01L2224/16225

Abstract: Microelectronic modules are described. In an embodiment, a microelectronic module includes a module substrate, a chip mounted onto the module substrate, and a semiconductor-based integrated passive device between the chip and the module substrate. The semiconductor-based integrated passive device may include an upper RDL stack-up with thicker wiring layers than a lower BEOL stack-up. The semiconductor-based integrated passive device may be further solder bonded or hybrid bonded with the chip.

公开(公告)号：US20240014178A1

公开(公告)日：2024-01-11

申请号：US18348641

申请日：2023-07-07

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L21/78 ,  H01L22/32 ,  H01L23/481 ,  H01L23/60 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/95001 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/30205

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.