公开(公告)号：GB2217059A

公开(公告)日：1989-10-18

申请号：GB8806859

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/38 ,  G06F15/78

Abstract: The system includes sub-systems each including a control processor, 110, a data transfer processor, 120, and a numerical processor, FP, 130, all running concurrently and each housing a plurality of external data interfaces controlled by the respective data transfer processor. The external interfaces include a first data interface for accessing main memory over a system bus and a second data interface including two high-bandwidth input ports and one high-bandwidth output port. Respective ports of second data interfaces are linked by local data buses to provide a data flow structure with a degree of pipelining and/or parallelism.

公开(公告)号：GB2217058A

公开(公告)日：1989-10-18

申请号：GB8806858

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F17/14

公开(公告)号：GB2217055A

公开(公告)日：1989-10-18

申请号：GB8806855

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT ,  WILSON MALCOLM ERIC ,  TREVETT NEIL FRANCIS

IPC: G06F9/24

Abstract: A multiprocessor subsystem, wherein each processor is separately microcoded so that the processors can run concurrently and asynchronously. To conserve lines and provide flexibility in specifying the subsystem configuration, a serial loop interface 225 A-E provides data access from a higher-level processor to all of the control stores 470 of the processors. To maximize the net bandwidth of this loop, each separate control store interfaces to it using a bank of serial/ parallel registers 610 which can load the instructions into the control store, or clock the instruction stream incrementally, or simply clock the instruction stream along as fast as possible. Thus, the bandwidth is used efficiently, and only a minimal number of instructions is required to access control storage for a given processor.

公开(公告)号：GB2215886A

公开(公告)日：1989-09-27

申请号：GB8806871

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/38 ,  G06F15/78

Abstract: The system provides a control processor operable asynchronously and concurrently with a numerical processor which performs arithmetic operations using a 32-bit word. The numerical processor interfaces to a cache memory through an interface including a cache bus, 144, which carries eight 32-bit words in parallel. The bus is multiplied down to 64-bit wide fast register files, 430, through a set of holding registers, 420, which play an important role in crossing between different clock domains in the numerical processing module. A double-word interface is provided from the register file toward the data bus although, from the numerical processing module the register tile appears to be only one word wide. This gives faster data transfer on the cache side of the register file even though some granularity is built into the address structure - even word addresses tend to map to even word addresses.

公开(公告)号：GB2215885A

公开(公告)日：1989-09-27

申请号：GB8806870

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/22 ,  G06F9/26

Abstract: An improved microcoded computer architecture, wherein the propagation delays of an unregistered microcode bit are avoided when the bit is not changing. The unregistered bit, A6, is applied via modification logic 2010 to multiplexer 1730, the output of which is registered at 1740 and fed back as the second input to the multiplexer. A second microcode bit, USEOLDA6, is registered at 1720 and used as the 'select' signal for the multiplexer. Propagation delays in logic 2010 are thus avoided by using the old A6 value from register 1740 when A6 is unchanging.

公开(公告)号：GB2215881A

公开(公告)日：1989-09-27

申请号：GB8806866

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F1/08

Abstract: A multiprocessor system includes a control processor 110 and a high-level data-transfer processor 120. Both of these processors are clocked by a shared variable-duration clock. The duration of the clock is adjusted on the fly, to accommodate whichever of the two processors needs the longest cycle time on that particular cycle. Thus, the control processor 110 and the data transfer processor 120 are enabled to run synchronously, even though they are concurrently running separate streams of instructions.

公开(公告)号：GB2215880A

公开(公告)日：1989-09-27

申请号：GB8806854

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT ,  TREVETT NEIL FRANCIS ,  WILSON MALCOLM ERIC

IPC: G06F9/22 ,  G06F9/26

Abstract: A numeric processing subsystem which has a dedicated data-transfer processor running concurrently and asynchronously with other processors. When accessing data generated externally (or at the interface controllers) which has less than the internal data width (32 bits), the top bit of the data is preferably replicated in hardware to fill the field. When a source is selected, such as the address generator 230 address port or data port, which drives only the lower sixteen bits, the sign/zero extend PLA, 216, is also activated so that the data are either sign-or-zero-extended up to the bus width of thirty-two bits. This provides correct sign and xero extension. This capability permits the 32-bit programming environment to dispose with word-instruction or byte-instructions.

公开(公告)号：GB2215876A

公开(公告)日：1989-09-27

申请号：GB8806850

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/38 ,  G06F15/78

Abstract: The processing system has an external interface controller 150, 160, 170, 180 arranged for connection to a host system. Three processors 110, 120, 130 are arranged to run concurrently. Of these processors a numerical processor, FF 130, runs asynchronously of the other two i.e. with a completely independent clock. So as not to lose the speed advantage of the numerical processor in connects to a data cache memory, 140, of one megabyte (or more) capacity through a wide band width cache bus 144, i.e. a bus at least 128 lines wide, where the memory parts are 32 bits wide.

公开(公告)号：GB2217064A

公开(公告)日：1989-10-18

申请号：GB8806864

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F9/38 ,  G06F15/78

Abstract: A multiprocessor system, wherein two asynchronous processors perform a handshaking interface using an asynchronous state machine. The state machine implements the state diagram shown, which includes an interlock. An output signal 'CP Done' or 'FP Done' from one processor de-asserts an 'FP Wait' or 'CP Wait' signal applied to the other processor.

公开(公告)号：GB2217063A

公开(公告)日：1989-10-18

申请号：GB8806863

申请日：1988-03-23

Applicant: BENCHMARK TECHNOLOGIES

Inventor： BALDWIN DAVID ROBERT

IPC: G06F5/06 ,  G06F7/78

Abstract: A LIFO memory organization is configured using a multilevel pipeline register. Control logic 3910 provides extremely high-speed LIFO operation, and also provides flexible access to the internal stages of the LIFO, by supplying selection signals to multiplexer 3922 for accessing selected register stages 3921.