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公开(公告)号：GB2217055A
公开(公告)日：1989-10-18
申请号：GB8806855
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： BALDWIN DAVID ROBERT , WILSON MALCOLM ERIC , TREVETT NEIL FRANCIS
IPC: G06F9/24
Abstract: A multiprocessor subsystem, wherein each processor is separately microcoded so that the processors can run concurrently and asynchronously. To conserve lines and provide flexibility in specifying the subsystem configuration, a serial loop interface 225 A-E provides data access from a higher-level processor to all of the control stores 470 of the processors. To maximize the net bandwidth of this loop, each separate control store interfaces to it using a bank of serial/ parallel registers 610 which can load the instructions into the control store, or clock the instruction stream incrementally, or simply clock the instruction stream along as fast as possible. Thus, the bandwidth is used efficiently, and only a minimal number of instructions is required to access control storage for a given processor.
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公开(公告)号：GB2215961A
公开(公告)日：1989-09-27
申请号：GB8806880
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： TREVETT NEIL FRANCIS , WILSON MALCOLM ERIC , LLOYD SARAH JANE
Abstract: A line having two directional components and a given length is clipped to display only a predetermined segment of the line by initializing any of a multiplier accumulator's output registers 410, 412, 414 with a predetermined intial value; loading a first input register 402 of a multiplier accumulator with the value of one component of the line; loading a second input register 404 of the multiplier accumulator with the value of the reciprocal of the other component of the line; causing the multiplier accumulator to multiply 406 the values in its first and second input registers; repeatedly adding the fractional part of the multiply to the first output register 410 while adding the overflow of the first output register in a second output register 412; repeatedly adding the integer part of the result of the multiply to the second register 412; and, drawing a point on a display device whenever the value in the second output register changes. The reciprocals for register 404 may come from a look-up table (502, fig 5). This method uses simple hardware, avoids divide operations and addresses the "Subset line" problem.
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公开(公告)号：GB2215880A
公开(公告)日：1989-09-27
申请号：GB8806854
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： BALDWIN DAVID ROBERT , TREVETT NEIL FRANCIS , WILSON MALCOLM ERIC
Abstract: A numeric processing subsystem which has a dedicated data-transfer processor running concurrently and asynchronously with other processors. When accessing data generated externally (or at the interface controllers) which has less than the internal data width (32 bits), the top bit of the data is preferably replicated in hardware to fill the field. When a source is selected, such as the address generator 230 address port or data port, which drives only the lower sixteen bits, the sign/zero extend PLA, 216, is also activated so that the data are either sign-or-zero-extended up to the bus width of thirty-two bits. This provides correct sign and xero extension. This capability permits the 32-bit programming environment to dispose with word-instruction or byte-instructions.
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公开(公告)号：GB2215959A
公开(公告)日：1989-09-27
申请号：GB8806877
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： TREVETT NEIL FRANCIS , WILSON MALCOLM ERIC
Abstract: A system having simultaneuosly accessable screen refresh (102) and off screen (104) memories which have the ability to perform image data translation and high speed copy operations. The off screen memory 104 and screen refresh memory 101 have independent address generation and the off screen memory 104 has XY offset logic 110 which can be used to simultaneously copy image data to and from the off screen memory with hardware address translation.
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公开(公告)号：GB2215957A
公开(公告)日：1989-09-27
申请号：GB8806875
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： TREVETT NEIL FRANCIS , WILSON MALCOLM ERIC
Abstract: A crossbar converter 800 to format 32 bit raster formatted I/O data into 5x4 patch formatted eight bit pixel data enables a 160 bit wide pixel data bus to be used so as to attain a high bandwidth for I/O devices. By using the wide pixel data bus and patch format for I/O, the facilities of an off screen memory 104, a screen refused memory 102 and an arbitary shape clipper 112 can be made available to process a real time video window on a high resolution, bit mapped display monitor. The crossbar converter 800 is bi-directional and comprises banks F1F0 baffers 912-920 accessed in series/parallel, in/out on parallel/series, in/out as appropriate using multiplexers 902-910 under the control of a (RAM or ROM) state machine 922.
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Patent Agency Ranking
公开(公告)号：GB2215955A
公开(公告)日：1989-09-27
申请号：GB8806873
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： TREVETT NEIL FRANCIS , WILSON MALCOLM ERIC
Abstract: A system includes a screen refresh (102) (i.e. on screen) and a simultaneously accessible off screen (104) memory. The system's preferred logic allows image address translation to be performed as the off screen memory is accessed, and enables high speed copy operations. Advantageously, video rate window processing is not required. The system enables video rams to be used for the screen refresh memory, whilst also allowing single ported rams to be used to hold undisplayed data. The off screen memory 104 enables fast and easy repair and movement of windows and provides the programmer with new solutions to many complex image manipulation problems. The system is designed with flexible source and destination control. Further, in one embodiment, image data can be quickly transferred in either direction between the screen refresh memory and the off screen memory with or without being manipulated by a graphics processor 100.
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公开(公告)号：GB2215951A
公开(公告)日：1989-09-27
申请号：GB8806843
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： TREVETT NEIL FRANCIS , WILSON MALCOLM ERIC
IPC: G06T1/20
Abstract: A system and method for performing raster operations in a patch access environment utilizes two or more source patches to produce an XY shifted destination patch. The XY shifted patch is then operated on by a write mask so that selected portions of the XY shifted patch are written into the destination. Specifically, the written portions of the XY shifted patch are present in the destination only where permitted by the write mask. Even though the present invention operates in a patch access environment, it can form a destination patch by merging groups of pixels not residing within the same patch boundaries. The shifting and merging used to form the XY shifted destination patch can be done on a patch plane basis or on a patch basis. The X shifting and merging effectively combines preselected contiguous columns of contigous patches. The X shifted patches are then shifted in the Y direction. A line of the XY shifted patches is stored in a memory. A second contiguous line of the XY shifted patches is also stored in the memory. The stored lines are merged and patches can be read out of the memory in a page mode fashion. Boolean or arithmetic operations can be performed between the XY shifted patch and pre-existing data within a destination patch area so as to produce the XY shifted destination patch.
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公开(公告)号：GB2215937A
公开(公告)日：1989-09-27
申请号：GB8806881
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： TREVETT NEIL FRANCIS , WILSON MALCOLM ERIC
Abstract: A system and method merges two or more analog video signals (Channels 1,2) under control of a third analog video signal 154. A standard video output from one processor's video signal digital to analog converter (DAC) is used as the control signal for the merging of two or more other video signals. This enables the video outputs of even highly diverse processing schemes to be easily merged. In its preferred embodiment, the system includes analog switching circuitry (140-142) which is used to mix the video outputs from two or more different systems. The system also includes circuitry (110) which converts the standard video output from a third processor into a large swing TTL signal which is used to control the analog switch.
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公开(公告)号：GB2217061A
公开(公告)日：1989-10-18
申请号：GB8806861
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： TREVETT NEIL FRANCIS , WILSON MALCOLM ERIC
Abstract: A computer system with an architectural feature which permits debugging. This system includes "claw" logic. The claw logic claws back control to the monitor task after one instruction in the user task has been run. The instruction which returns control to the user task requests a claw interrupt. This is delayed by one cycle so that the interrupt occurs on the first instruction executed in the user task. So control is restored to the monitor task before the second instruction in the user task is executed. This means that the monitor process (used during debugging) can single-step the application program, without the monitor program itself having to be single-stepped.
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公开(公告)号：GB2215960A
公开(公告)日：1989-09-27
申请号：GB8806879
申请日：1988-03-23
Applicant: BENCHMARK TECHNOLOGIES
Inventor： TREVETT NEIL FRANCIS , WILSON MALCOLM ERIC , LLOYD SARAH JANE
Abstract: A method of linear interpolation over a line having a given length comprising the steps of initializing the multiplier accumulators output registers with predetermined initial values 410, 412 [e.g. with the initial rounding value and the starting value for one of the coordinates (e.g. Y), respectively]; loading a first input register 402 of the multiplier accumulator with a value equal to the incremental change (e.g. DELTA Y=5) in the output value over the length of the line; loading a second input register 404 of the multiplier accumulator with a value (1/N) equal to the reciprocal of the length of the line (N); causing the multiplier 406 to multiply the values (eg DELTA Y and 1/N) at its first and second inputs; accumulating the fractional part of the result of the multiplication in a first output register 410; accumulating the interger part of the result of the multiplication added with the overflow of the first output register in a second output register, 412, whereby and accumulated result is formed. The overflow is accumulated in a third output register, 414, and overflows to the integral register. For Gouraud shading of a line, one of the input registers is loaded with colour change along a line and the other with reciprocal of line length. An output register, 412, is initialised with a start colour.
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