公开(公告)号：WO1996019793A1

公开(公告)日：1996-06-27

申请号：PCT/US1995016012

申请日：1995-12-19

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  BRIL, Vlad ,  EGLIT, Alexander ,  KENKARE, Sagar, Waman

IPC: G09G01/16

CPC classification number: G09G5/366 ,  G09G5/14 ,  G09G5/393 ,  G09G5/395 ,  G09G5/40

Abstract: A video controller is provided which reduces the effect of page misses during memory access. A video port FIFO is provided for buffering data from a video port to a display memory. A CRT FIFO is provided for buffering data from a display memory to a display. If, during a video port FIFO cycle, a page miss is encountered, the video port FIFO cycle is terminated and processing passes to a CRT FIFO CYCLE. If a page miss is encountered during a CRT FIFO CYCLE, the subsequent video port FIFO cycle will be shortened by a number of memory cycles to compensate for the additional memory cycles required by the page miss. Additional data accumulated in the video port FIFO may be transferred to the display memory during a retrace interval. In this manner, memory bandwidth is optimized by removing a non-aligned page miss as the worst case of memory bandwidth utilization.

Abstract translation: 提供了一种视频控制器，可以减少存储器访问期间页错误的影响。 提供视频端口FIFO用于将数据从视频端口缓冲到显示存储器。 提供CRT FIFO用于将数据从显示存储器缓冲到显示器。 如果在视频端口FIFO周期期间遇到页面未命中，则视频端口FIFO周期终止，并且处理转到CRT FIFO CYCLE。 如果在CRT FIFO CYCLE期间遇到页错失，则随后的视频端口FIFO周期将缩短多个存储周期，以补偿页错过所需的附加存储器周期。 视频端口FIFO中积累的附加数据可以在回扫间隔期间被传送到显示存储器。 以这种方式，通过消除不对齐的页面遗漏作为存储器带宽利用的最坏情况来优化存储器带宽。

公开(公告)号：WO1996013004A1

公开(公告)日：1996-05-02

申请号：PCT/US1995013541

申请日：1995-10-20

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  ZOOK, Christopher, P.

IPC: G06F12/06

CPC classification number: G06F11/1068 ,  G06F7/726 ,  G06F11/10 ,  G06F11/1004 ,  H03M13/00 ,  H03M13/15 ,  H03M13/35

Abstract: An error correction system (10) is provided for correcting up to two bits per sector stored in a solid state non-volatile memory (12) which emulates a disk drive. The error correction system (10) includes an ECC/remainder generator (100), a bank of remainder registers (102), and a calculation circuit (104), all under supervision of a controller (106). During a write-to-memory operation, error correction system (10) generates ECC bytes for storage in the memory (12). In a write operation, an entire sector acquired from memory (12) is used to generate ECC check remainder bytes REM0 - REM3. The check remainder bytes REM0 - REM3 are utilized to generate syndromes S1, S3 and a factor S8; the syndromes in turn being used to obtain either one or two error location positions ( alpha , alpha ).

Abstract translation: 提供纠错系统（10），用于校正存储在模拟盘驱动器的固态非易失性存储器（12）中的每扇区多达两位。 纠错系统（10）包括ECC控制器（106）的ECC /余数发生器（100），余数寄存器组（102）和计算电路（104）。 在写入存储器操作期间，纠错系统（10）产生用于存储在存储器（12）中的ECC字节。 在写入操作中，使用从存储器（12）获取的整个扇区来产生ECC校验余数字节REM0-REM3。 检查余数字节REM0-REM3用于产生综合征S1，S3和因子S8; 综合证据依次用于获得一个或两个错误位置位置（α，α）。

公开(公告)号：WO1996010889A1

公开(公告)日：1996-04-11

申请号：PCT/US1995012476

申请日：1995-09-29

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  SUNG, Chih-Ta ,  CHAN, Tzoyao ,  CHANG, Richard ,  ROSENAU, Mark, A. ,  ORT, Jeffrey, G. ,  DAUM, Daniel, T. ,  SUN, Yuanyuan

IPC: H04N07/52

CPC classification number: H04N9/8216 ,  G09G5/393 ,  G11B20/00007 ,  G11B20/10527 ,  G11B27/10 ,  G11B27/105 ,  G11B27/3027 ,  G11B27/3036 ,  G11B2220/213 ,  G11B2220/2545 ,  H04N5/775 ,  H04N5/85 ,  H04N9/8042 ,  H04N9/8063 ,  H04N9/87 ,  H04N19/132 ,  H04N19/42 ,  H04N19/423 ,  H04N19/427 ,  H04N19/587 ,  H04N19/61 ,  H04N21/4143 ,  H04N21/4305 ,  H04N21/4307

Abstract: A multimedia system including an audio/video decoder/decompresser for decoding/decompressing a compressed encoded audio/video data stream to generate video images for display and audio signals for audible reproduction. The multimedia system includes an integrated system and video decoder with an audio/video synchronization circuit for substantially synchronizing the display of video images with audio playback. A method is described for detecting when the playback of audio and the display of video images are out of synchronization. The circuitry includes three programmable registers, a finite state machine and one full adder using an audio presentation time stamp and the video presentation time stamp. The method uses a rounded programmable bias value which is compared with the difference between the video presentation time stamp and the audio presentation time stamp. The difference may include the latency delay of the audio and video display devices to more properly reflect the synchronization status between audio and video. The circuit area used by the circuitry has been minimized by selective rounding or truncation of the audio presentation time stamp and the video presentation time stamp without sacrificing the accuracy or speed of determining the synchronization between audio and video.

Abstract translation: 一种多媒体系统，包括音频/视频解码器/解压缩器，用于解码/解压缩压缩的编码音频/视频数据流以产生用于显示的视频图像和用于可听再现的音频信号。 多媒体系统包括具有音频/视频同步电路的集成系统和视频解码器，用于使视频图像的显示与音频回放基本上同步。 描述了一种用于检测音频的重放和视频图像的显示何时不同步的方法。 该电路包括三个可编程寄存器，有限状态机和一个使用音频呈现时间戳和视频呈现时间戳的全加器。 该方法使用舍入的可编程偏置值，其与视频呈现时间戳和音频呈现时间戳之间的差进行比较。 差异可以包括音频和视频显示设备的延迟延迟以更恰当地反映音频和视频之间的同步状态。 通过选择性舍入或截断音频呈现时间戳和视频呈现时间戳，电路所使用的电路区域已经被最小化，而不牺牲确定音频和视频之间的同步的准确性或速度。

公开(公告)号：WO1996010887A1

公开(公告)日：1996-04-11

申请号：PCT/US1995012904

申请日：1995-09-29

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  KEENE, David ,  YANG, Jimmy ,  CHANG, Kevin

IPC: H04N05/44

CPC classification number: H04N7/012 ,  G09G5/395 ,  G09G2310/0224 ,  G09G2340/0414

Abstract: An apparatus and method are provided for reducing flicker and/or vertically scaling an interlaced video image. In a first embodiment, a sequence controller (102) selectively addresses a video memory to retrieve pixel data from adjacent scan lines. The pixel data is multiplexed and converted into RGB data in a look up table (107) and stored in upper and lower latches (108, 109) as upper and lower pixel data. The upper and lower pixel data is then weighted using a predetermined weighting scheme to produce hybrid pixel color data for an even or odd field. By reducing relative contrast between even and odd field lines, flicker is reduced. In a second embodiment, vertical resolution is reduced, for example, from 480 lines to 400 lines, by applying a series of weighting schemes or filters to weight data from six input lines into five output lines. To reduce flicker in the output lines, data from adjacent lines may be weighted to reduce relative contrast. Due to the 6:5 reduction, a discontinuity in the output lines may exist where adjacent line data is not weighted. Luminance data from a third adjacent line may be weighted with pixel data from adjacent lines to reduce flicker at the discontinuity.

Abstract translation: 提供了一种用于减少隔行扫描和/或垂直缩放隔行视频图像的装置和方法。 在第一实施例中，序列控制器（102）选择性地寻址视频存储器以从相邻扫描线检索像素数据。 像素数据被多路复用并在查询表（107）中被转换成RGB数据并存储在上和下锁存器（108,109）中作为上和下像素数据。 然后使用预定的加权方案对上下像素数据进行加权，以产生用于偶数或奇数场的混合像素颜色数据。 通过减少偶数和奇数场线之间的相对对比度，闪烁减小。 在第二实施例中，通过应用一系列加权方案或滤波器将来自六条输入线的数据加权到五条输出线中，垂直分辨率例如从480线降低到400线。 为了减少输出线中的闪烁，来自相邻线的数据可以被加权以减小相对对比度。 由于6：5的减少，相邻行数据不加权的情况下可能存在输出行的不连续性。 来自第三相邻行的亮度数据可以用来自相邻行的像素数据进行加权，以减少不连续处的闪烁。

公开(公告)号：WO1996008875A1

公开(公告)日：1996-03-21

申请号：PCT/US1995012087

申请日：1995-09-15

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  ZOOK, Christopher, P.

IPC: H03M13/00

CPC classification number: G06F7/726 ,  G06F11/10 ,  G06F11/1004 ,  G11B20/10527 ,  G11B20/18 ,  G11B20/1833 ,  H03M13/00 ,  H03M13/15 ,  H03M13/151 ,  H03M13/35

Abstract: A bit-oriented error correction calculation circuit performs numerous mathematical operations including bit-oriented convolutions, inversions, multiplications, additions, and bi-directional basis conversions. The circuit includes three banks of registers (400, 401, 402) connected as a convolution circuit to produce a sequence of inner products with respect to the first bank of registers (400) and the second bank of registers (401). Each of the banks of registers (400, 401) has a bank loading switch (440, 441, 442) connected to a serial input terminal thereof for loading a selected one of a plurality of serial multibit values into the banks, including selective gating of feedback signals from respective feedback circuits (450, 452) in registers (400, 402) and (inter alia) constant values. The values of the feedback multipliers are selectively changeable in accordance with a field length of the value involved in error correction of data. Further included are a summation circuit (320), a comparison circuit (360), and a bi-directional conversion unit for converting an m-bit input value from an input basis representation to an output basis representation.

Abstract translation: 面向位的纠错计算电路执行许多数学运算，包括面向位的卷积，反转，乘法，相加和双向基础转换。 电路包括作为卷积电路连接的三组寄存器（400,401,402），以产生相对于第一组寄存器（400）和第二寄存器组（401）的内积序列。 每个寄存器组（400,401）具有连接到其串行输入端的组负载开关（440,441,442），用于将多个串行多位值中选择的一个加载到存储体中，包括选择性选通 来自寄存器（400,402）中的各个反馈电路（450,452）和（特别是）常数值的反馈信号。 反馈乘法器的值可以根据涉及数据误差校正的值的场长度来选择性地变化。 进一步包括求和电路（320），比较电路（360）和用于将m位输入值从输入基础表示转换为输出基础表示的双向转换单元。

公开(公告)号：WO1996008773A2

公开(公告)日：1996-03-21

申请号：PCT/US1995011692

申请日：1995-09-15

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  BEZZANT, Daniel, G. ,  SMITH, Stephen, A. ,  NOOKALA, Narasimha, R. ,  NARAYANAN, Puducode, S. ,  DIKSHIT, Ashutosh, S.

IPC: G06F13/28

CPC classification number: G06F13/4068 ,  G06F13/28

Abstract: A PCMCIA host adapter includes the capability to master a non-DMA system bus and control a DMA data transfer between a DMA capable peripheral and the internal system memory. A peripheral can be coupled to the system through a PCMCIA card plugged into a PCMCIA expansion slot. A DMA controller coupled to the PCMCIA expansion slot through a PCMCIA bus controls a DMA transfer between the internal system memory and the peripheral. A bus master disables the CPU and takes control of the system bus during a DMA data transfer. In an alternative embodiment, the PCMCIA host adapter can be used with either a system having a system bus with DMA capability or with a system having a system bus without DMA capability. In this alternate embodiment if the system bus has DMA capability, the PCMCIA host adapter effectively passes the DMA signals between the peripheral and the system bus. If the system bus does not have DMA capability then the DMA controller and the bus master work to disable the CPU and take control of the system bus during a DMA data transfer. The DMA controller then controls the transfer of data between the peripheral and the internal system memory.

Abstract translation: PCMCIA主机适配器包括掌握非DMA系统总线并控制DMA能力外设与内部系统存储器之间的DMA数据传输的功能。 外设可以通过插入PCMCIA扩展槽的PCMCIA卡耦合到系统。 通过PCMCIA总线耦合到PCMCIA扩展槽的DMA控制器控制内部系统存储器和外设之间的DMA传输。 总线主控器在DMA数据传输期间禁用CPU并控制系统总线。 在替代实施例中，PCMCIA主机适配器可以与具有具有DMA能力的系统总线的系统或具有不具有DMA能力的系统总线的系统一起使用。 在该替代实施例中，如果系统总线具有DMA能力，则PCMCIA主机适配器有效地在外围设备和系统总线之间传递DMA信号。 如果系统总线不具有DMA能力，则DMA控制器和总线主机可以在DMA数据传输期间禁用CPU并控制系统总线。 然后，DMA控制器控制外设和内部系统存储器之间的数据传输。

公开(公告)号：WO1995012850A1

公开(公告)日：1995-05-11

申请号：PCT/US1994012136

申请日：1994-10-18

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  ZOOK, Christopher, P.

IPC: G06F11/10

CPC classification number: G06F11/1004 ,  G06F11/10 ,  H03M13/151 ,  H03M13/35

Abstract: A Reed-Solomon decoder (199) processes a codeword containing n m-bit symbols to determine coefficients of an error locator polynomial sigma (x), and thereafter generates an error evaluator polynomial omega (x). The decoder comprises a bank (B103) of syndrome registers (103) for storing syndrome values; a bank (B101) of error locator registers (101) for accumulating therein coefficients of an error locator polynomial sigma (x); and, a bank (B102) of intermediate registers (102) for accumulating therein coefficients of an intermediate polynomial tau (x). The decoder (199) further includes a register update circuit (50) which, for a given codeword, conducts two-phased error locator iterations in order to update values in the error locator registers and the intermediate registers. In contrast to prior art techniques, the register update circuit (50) of the present invention updates coefficients of the intermediate polynomial tau (x) during the first phase of each error locator iteration, and updates coefficients of the error locator polynomial sigma (x) during the second phase of each error loctor iteration. In further contrast, the decoder (199) of the present invention requires only one bank of error locator registers (101) and one bank of intermediate registers (102) and facilitates serial data shifting rather than parallel data transfer, thereby reducing circuit real estate.

Abstract translation: 里德 - 所罗门解码器（199）处理包含n个m位符号的码字以确定误差定位多项式sigma（x）的系数，然后生成误差评估器多项式ω（x）。 解码器包括用于存储校正子值的校正子寄存器（103）的存储体（B103） 错误定位器寄存器（101）的存储体（B101），用于在其中累积误差定位多项式σ（x）的系数; 以及用于在其中累积中间多项式tau（x）的系数的中间寄存器（102）的存储体（B102）。 解码器（199）还包括寄存器更新电路（50），对于给定的代码字，对所述错误定位器寄存器和所述中间寄存器中的值进行更新，所述寄存器更新电路（50）进行两相误差定位器迭代。 与现有技术相反，本发明的寄存器更新电路（50）在每个错误定位器迭代的第一阶段更新中间多项式tau（x）的系数，并且更新误差定位多项式σ（x）的系数， 在每个错误代码迭代的第二阶段。 进一步的对比是，本发明的解码器（199）只需要一组误差定位器寄存器（101）和一组中间寄存器（102），并且便于串行数据移位而不是并行数据传输，从而减少电路的不动产。

公开(公告)号：WO1995006941A1

公开(公告)日：1995-03-09

申请号：PCT/US1994010019

申请日：1994-08-31

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  ROMANO, Paul, M.

IPC: G11B05/54

CPC classification number: G11B5/54

Abstract: A voice coil motor (VCM) control circuit (10) controls the motor operation to position a disk drive head and actuator arm assembly (202). A data processor (220) is continuously updated with the current position and relative radial velocity of the disk drive head (206) and actuator arm assembly (208). The data processor (220) provides signals to a digital-to-analog converter (DAC) of the VCM control circuit (10) representative of the amount of energy necessary to move the head and actuator arm assembly to a parking position from a current operating position.

Abstract translation: 音圈电机（VCM）控制电路（10）控制电动机操作以定位盘驱动头和致动器臂组件（202）。 数据处理器（220）以盘驱动头（206）和致动器臂组件（208）的当前位置和相对径向速度连续地更新。 数据处理器（220）向VCM控制电路（10）的数模转换器（DAC）提供信号，该数字模拟转换器（DAC）代表从当前操作中移动头部和致动器臂组件到停车位置所需的能量的量 位置。

公开(公告)号：WO1994018670A1

公开(公告)日：1994-08-18

申请号：PCT/US1994001084

申请日：1994-01-31

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  BEHRENS, Richard, T. ,  ANDERSON, Kent, D. ,  ARMSTRONG, Alan ,  DUDLEY, Trent ,  FOLAND, Bill ,  GLOVER, Neal ,  KING, Larry

IPC: G11B05/09

CPC classification number: G11B20/10055 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1258 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B2020/1476 ,  H03M13/31

Abstract: A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control (32), timing recovery (34), sequence detection (40), RLL (1, 7) encoding (48) and RLL (1, 7) decoding (28), and channel quality measurement (46) is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection (40). These characteristics, together with error-tolerant sync mark detection (26) and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery.

Abstract translation: 具有提供数字增益控制（32），定时恢复（34），序列检测（40），RLL（1,7）编码（48）和RLL（1,7）的单芯片集成电路数字部分的同步读通道， 解码（28）和信道质量测量（46）。 集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测提供解码数据的能力（40）。 这些特性以及容错同步标记检测（26）以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略来最大限度地提高数据恢复的可能性。

公开(公告)号：WO1994008394A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009110

申请日：1993-09-24

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  BEHRENS, Richard, T. ,  DUDLEY, Trent ,  GLOVER, Neal ,  WELLAND, David, R.

IPC: H03D03/24

CPC classification number: G11B20/10037 ,  G11B20/1403 ,  H03D13/005 ,  H03L7/091 ,  H04L7/0334 ,  H04L7/04 ,  H04L7/046 ,  H04L7/10

Abstract: A timing circuit having an analog to digital converter (206) to sample an analog signal, a controlled oscillator for controlling sample times of the analog to digital converter, a circuit (312) to detect pulses in the analog signal, a phase error circuit to subtract one of two samples from the other to create a phase error measurement and a frequency error measurement. The two samples are taken from either side of a pulse. The phase error measurement is used by the controlled oscillator to adjust the sample timing to take samples at desired locations on the pulse. The circuit also contains constant values used to compensate for the pulse being asymmetrical and to compensate for other pulses that occur close to the detected pulse. The circuit also inserts a known frequency in place of the analog signal to establish a frequency of the controlled oscillator.

Abstract translation: 一种具有用于对模拟信号进行采样的模数转换器（206）的定时电路，用于控制模数转换器的采样时间的受控振荡器，用于检测模拟信号中的脉冲的电路（312），相位误差电路 从另一个样本中减去一个样本，以创建相位误差测量和频率误差测量。 两个样本取自脉冲的任一侧。 相位误差测量由受控振荡器用于调整采样定时以在脉冲的所需位置采样。 电路还包含用于补偿不对称脉冲的常数值，并补偿靠近检测到的脉冲发生的其他脉冲。 电路还插入已知频率代替模拟信号以建立受控振荡器的频率。